A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR
- Author
- JIPENG LI1 ; AHN, Gil-Cho2 ; CHANG, Dong-Young3 ; MOON, Un-Ku2
[1] East Coast Lab (ECL) Design Center, National Semiconductor Inc, Salem, NH 03079-4863, United States
[2] School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331-3211, United States
[3] Texas Instruments Incorporated, Tucson, AZ 85706, United States - Conference title
- 2004 Symposium on VLSI Circuits
- Conference name
- 2004 Symposium on VLSI Circuits (Honolulu, HI 2004-06-17)
- Author (monograph)
- GIESEKE, Bruce (Editor)1 ; KURODA, Tadahiro (Editor)2
[1] Advanced Micro Devices, Sunnyvale, CA 94088-3453, United States
[2] Keio University, Yokohama, 223-8522, Japan - Source
IEEE journal of solid-state circuits. 2005, Vol 40, Num 4, pp 960-969, 10 p ; ref : 24 ref
- CODEN
- IJSCBC
- ISSN
- 0018-9200
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Conference Paper
- Language
- English
- Author keyword
- Algorithmic ADC background digital calibration low power low voltage pipelined ADC two channel ADC architecture
- Keyword (fr)
- Algorithme Algorithmique Amplificateur opérationnel Basse tension Condensateur Consommation énergie électrique Convertisseur AN Désadaptation Echantillonnage Electronique faible puissance Gain Horloge Matrice formage Prototype Rapport signal bruit Résistance électrique Technologie MOS complémentaire Traitement pipeline Plage dynamique sans parasite Rapport signal bruit distorsion
- Keyword (en)
- Algorithm Algorithmics Operational amplifier Low voltage Capacitor Power consumption AD converter Mismatching Sampling Low-power electronics Gain Clock Die Prototype Signal to noise ratio Resistor Complementary MOS technology Pipeline processing Spurious free dynamic range Signal to noise and distortion ratio
- Keyword (es)
- Algoritmo Algorítmica Amplificador operacional Baja tensión Condensador Convertidor AN Desadaptación Muestreo Ganancia Reloj Matriz formadora Prototipo Relación señal ruido Resistencia eléctrica(componente) Tecnología MOS complementario
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03D Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F09 Dielectric, amorphous and glass solid devices
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A4 Signal convertors
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 16720386
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/JSSC.2004.842866 
https://dx.doi.org/10.1109/JSSC.2004.842866
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