Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays
- Author
- HUR, J. Y1 ; GOOSSENS, K2 ; MHAMDI, L3 ; WAHLAH, M. A1
[1] Computer Engineering Laboratory, TU Delft, Netherlands
[2] Faculty of Electrical Engineering, TU Eindhoven, Netherlands
[3] School of Electronic and Electrical Engineering, University of Leeds, West Yorkshire, Leeds LS2 9JT, United Kingdom - Source
IET computers & digital techniques (Print). 2012, Vol 6, Num 6, pp 396-405, 10 p ; ref : 29 ref
- ISSN
- 1751-8601
- Scientific domain
- Electronics; Computer science; Telecommunications
- Publisher
- Institution of Engineering and Technology, Stevenage
- Publication country
- United Kingdom
- Document type
- Article
- Language
- English
- Keyword (fr)
- Analyse coût efficacité Analyse fonctionnelle Architecture reconfigurable Architecture réseau Circuit intégré Compression image Dispositif onde acoustique volume Etude cas Evaluation performance File attente Implémentation Interconnexion Processeur Réseau interconnexion Réseau porte programmable Résonateur onde acoustique Système attente Système sur puce
- Keyword (en)
- Cost efficiency analysis Functional analysis Reconfigurable architectures Network architecture Integrated circuit Image compression Bulk acoustic wave devices Case study Performance evaluation Queue Implementation Interconnection Processor Interconnection network Field programmable gate array Acoustic wave resonator Queueing system System on a chip
- Keyword (es)
- Análisis costo eficacia Análisis funcional Arquitectura red Circuito integrado Compresión imagen Estudio caso Evaluación prestación Fila espera Implementación Interconexión Procesador Red interconexión Red puerta programable Resonador onda acústica Sistema fila espera Sistema sobre pastilla
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F14 Acoustic wave devices, piezoelectric and piezoresistive devices
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A6 Digital circuits
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 26838785
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1049/iet-cdt.2011.0169 
https://dx.doi.org/10.1049/iet-cdt.2011.0169
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1049\/iet-cdt.2011.0169\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:9:\"\u0000*\u0000jtitle\";s:42:\"IET computers & digital techniques (Print)\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2012\";s:9:\"\u0000*\u0000volume\";s:1:\"6\";s:8:\"\u0000*\u0000issue\";s:1:\"6\";s:8:\"\u0000*\u0000spage\";s:3:\"396\";s:8:\"\u0000*\u0000epage\";s:3:\"405\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1751-8601\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:3:\"HUR\";s:10:\"\u0000*\u0000aufirst\";s:4:\"J. Y\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:3:{i:0;s:11:\"GOOSSENS, K\";i:1;s:9:\"MHAMDI, L\";i:2;s:12:\"WAHLAH, M. A\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:41:\"Institution of Engineering and Technology\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1049\/iet-cdt.2011.0169\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:9:\"\u0000*\u0000jtitle\";s:42:\"IET computers & digital techniques (Print)\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2012\";s:9:\"\u0000*\u0000volume\";s:1:\"6\";s:8:\"\u0000*\u0000issue\";s:1:\"6\";s:8:\"\u0000*\u0000spage\";s:3:\"396\";s:8:\"\u0000*\u0000epage\";s:3:\"405\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1751-8601\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:3:\"HUR\";s:10:\"\u0000*\u0000aufirst\";s:4:\"J. Y\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:3:{i:0;s:11:\"GOOSSENS, K\";i:1;s:9:\"MHAMDI, L\";i:2;s:12:\"WAHLAH, M. A\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:41:\"Institution of Engineering and Technology\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"UnpaywallOpenUrl\":35:{s:8:\"\u0000*\u0000email\";s:27:\"assistance-portail@inist.fr\";s:6:\"\u0000*\u0000fmt\";N;s:6:\"\u0000*\u0000doi\";s:25:\"10.1049\/iet-cdt.2011.0169\";s:6:\"\u0000*\u0000pii\";N;s:7:\"\u0000*\u0000pmid\";N;s:9:\"\u0000*\u0000atitle\";N;s:9:\"\u0000*\u0000jtitle\";N;s:9:\"\u0000*\u0000stitle\";N;s:7:\"\u0000*\u0000date\";N;s:9:\"\u0000*\u0000volume\";N;s:8:\"\u0000*\u0000issue\";N;s:8:\"\u0000*\u0000spage\";N;s:8:\"\u0000*\u0000epage\";N;s:8:\"\u0000*\u0000pages\";N;s:7:\"\u0000*\u0000issn\";N;s:8:\"\u0000*\u0000eissn\";N;s:9:\"\u0000*\u0000aulast\";N;s:10:\"\u0000*\u0000aufirst\";N;s:9:\"\u0000*\u0000auinit\";N;s:10:\"\u0000*\u0000auinitm\";N;s:5:\"\u0000*\u0000au\";N;s:9:\"\u0000*\u0000aucorp\";N;s:7:\"\u0000*\u0000isbn\";N;s:8:\"\u0000*\u0000coden\";N;s:8:\"\u0000*\u0000genre\";N;s:7:\"\u0000*\u0000part\";N;s:9:\"\u0000*\u0000btitle\";N;s:8:\"\u0000*\u0000title\";N;s:8:\"\u0000*\u0000place\";N;s:6:\"\u0000*\u0000pub\";N;s:10:\"\u0000*\u0000edition\";N;s:9:\"\u0000*\u0000tpages\";N;s:9:\"\u0000*\u0000series\";N;s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";N;}"
Unpaywall access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1049\/iet-cdt.2011.0169\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:9:\"\u0000*\u0000jtitle\";s:42:\"IET computers & digital techniques (Print)\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2012\";s:9:\"\u0000*\u0000volume\";s:1:\"6\";s:8:\"\u0000*\u0000issue\";s:1:\"6\";s:8:\"\u0000*\u0000spage\";s:3:\"396\";s:8:\"\u0000*\u0000epage\";s:3:\"405\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1751-8601\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:3:\"HUR\";s:10:\"\u0000*\u0000aufirst\";s:4:\"J. Y\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:3:{i:0;s:11:\"GOOSSENS, K\";i:1;s:9:\"MHAMDI, L\";i:2;s:12:\"WAHLAH, M. A\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:41:\"Institution of Engineering and Technology\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:11:\"BaseOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1049\/iet-cdt.2011.0169\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:9:\"\u0000*\u0000jtitle\";s:42:\"IET computers & digital techniques (Print)\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2012\";s:9:\"\u0000*\u0000volume\";s:1:\"6\";s:8:\"\u0000*\u0000issue\";s:1:\"6\";s:8:\"\u0000*\u0000spage\";s:3:\"396\";s:8:\"\u0000*\u0000epage\";s:3:\"405\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1751-8601\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:3:\"HUR\";s:10:\"\u0000*\u0000aufirst\";s:4:\"J. Y\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:3:{i:0;s:11:\"GOOSSENS, K\";i:1;s:9:\"MHAMDI, L\";i:2;s:12:\"WAHLAH, M. A\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:41:\"Institution of Engineering and Technology\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Base Search access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1049\/iet-cdt.2011.0169\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:9:\"\u0000*\u0000jtitle\";s:42:\"IET computers & digital techniques (Print)\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2012\";s:9:\"\u0000*\u0000volume\";s:1:\"6\";s:8:\"\u0000*\u0000issue\";s:1:\"6\";s:8:\"\u0000*\u0000spage\";s:3:\"396\";s:8:\"\u0000*\u0000epage\";s:3:\"405\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1751-8601\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:3:\"HUR\";s:10:\"\u0000*\u0000aufirst\";s:4:\"J. Y\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:3:{i:0;s:11:\"GOOSSENS, K\";i:1;s:9:\"MHAMDI, L\";i:2;s:12:\"WAHLAH, M. A\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:94:\"Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:41:\"Institution of Engineering and Technology\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
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