Post-processing of clock trees via wiresizing and buffering for robust design
- Author
- PULLELA, S1 ; MENEZES, N1 ; PILEGGI, L. T1
[1] Department of Electrical and Computer Engineering, The University of Texas, Austin, TX 78712, United States - Source
IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 6, pp 691-701 ; ref : 20 ref
- CODEN
- ITCSDI
- ISSN
- 0278-0070
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Algorithme Circuit intégré Conception assistée Interconnexion Synthèse circuit
- Keyword (en)
- Algorithm Integrated circuit Computer aided design Interconnection Circuit synthesis
- Keyword (es)
- Algoritmo Circuito integrado Concepción asistida Interconección Síntesis circuito
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 3178741
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/43.503938 
https://dx.doi.org/10.1109/43.503938
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