Systolic implementation of FIR decimators and interpolators
- Author
- ABDEL-RAHEEM, E; EL-GUIBALY, F; ANTONIOU, A
Univ. Victoria, dep. electrical computer eng., Victoria BC V8W 3P6, Canada - Source
IEE proceedings. Circuits, devices and systems. 1994, Vol 141, Num 6, pp 489-492 ; ref : 19 ref
- ISSN
- 1350-2409
- Scientific domain
- Electronics
- Publisher
- Institution of Electrical Engineers, Stevenage
- Publication country
- United Kingdom
- Document type
- Article
- Language
- English
- Keyword (fr)
- Circuit VLSI Décimation Filtre réponse impulsion finie Implémentation Interpolateur Processeur tableau Réseau systolique
- Keyword (en)
- VLSI circuit Decimation Finite impulse response filter Implementation Interpolator Array processor Systolic network
- Keyword (es)
- Circuito VLSI Decimación Filtro respuesta impulsión acabada Ejecución Interpolador Procesador panel Red sistólica
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 3371263
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1049/ip-cds:19941525 
https://dx.doi.org/10.1049/ip-cds:19941525
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