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An 800MHz embedded DRAM with a concurrent refresh modeKIRIHATA, Toshiaki; PARRIES, Paul; WORDEMAN, Matt et al.IEEE International Solid-State Circuits Conference. 2004, pp 206-207, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Architecture and circuit techniques for a reconfigurable memory blockKEN MAI; HO, Ron; ALON, Elad et al.IEEE International Solid-State Circuits Conference. 2004, pp 500-501, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

An experimental 256Mb non-volatile DRAM with cell plate boosted programming techniqueAHN, J-H; HONG, S-H; CHOI, J-H et al.IEEE International Solid-State Circuits Conference. 2004, pp 42-43, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipeliningBARTH, J; ANAND, D; DREIBELBIS, J et al.IEEE International Solid-State Circuits Conference. 2004, pp 204-205, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 0.6V 205MHz 19.5ns tRC 16Mb embedded DRAMHARDEE, K; JONES, F; TANIGUCHI, K et al.IEEE International Solid-State Circuits Conference. 2004, pp 200-201, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 1.6Gb/s/pin double-data-rale SDRAM with wave-pipelined CAS latency controlLEE, Sang-Bo; JANG, Seong-Jin; HEO, Hyoung-Jo et al.IEEE International Solid-State Circuits Conference. 2004, pp 210-211, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

At-speed interconnect test and diagnosis of external memories on a systemKIM, Heon C; JUN, Hong-Shin; XINLI GU et al.International Test Conference. 2004, pp 156-162, isbn 0-7803-8580-2, 1Vol, 7 p.Conference Paper

Low-temperature operation of silicon dynamic random-access memoriesWYNS, P; ANDERSON, R. L.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 8, pp 1423-1428, issn 0018-9383, 6 p.Article

Programmable at-speed array and functional BIST for embedded DRAM LSIKUME, Masaji; UEHARA, Katsutoshi; ITAKURA, Minoru et al.International Test Conference. 2004, pp 988-996, isbn 0-7803-8580-2, 1Vol, 9 p.Conference Paper

Logic based embedded dram technologiesMALLARDEAU, Catherine.Proceedings - Electrochemical Society. 2003, pp 133-135, issn 0161-6374, isbn 1-56677-376-8, 3 p.Conference Paper

A 128K×8 70-MHz multiport video RAM with auto register reload and 8×4 block WRITE featurePINKHAM, R; RUSSELL, D; GUILLEMAUD, A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1133-1139, issn 0018-9200Article

Dual-ported memorySCAYSBROOK, F. F.Review of scientific instruments. 1986, Vol 57, Num 1, pp 122-123, issn 0034-6748Article

Interfacing multi-processors using devices with dual-port RAMGONZALES, D. R.Microelectronics. 1985, Vol 16, Num 3, pp 5-12, issn 0026-2692Article

All points addressable raster display memoryMATICK, R; LING, D. T; GUPTA, S et al.IBM journal of research and development. 1984, Vol 28, Num 4, pp 379-392, issn 0018-8646Article

Mainstream memory technologies in deep submicronNATARAJAN, Sreedhar; ALVANDPOUR, Atila.Mediterranean electrotechnical conference. 2004, isbn 0-7803-8271-4, 3Vol, Vol.1, 175-178Conference Paper

A 130nm 1.1V 143MHz SRAM-like. Embedded DRAM COMPILER with dual asymmetric bit line sensing scheme and quiet unselected IO schemeNOH, K. J; CHOI, Y. J; JOO, J. D et al.Symposium on VLSI Circuits. 2003, pp 190-191, isbn 0-7803-8287-0, 1Vol, 2 p.Conference Paper

On the design of hybrid DRAM/SRAM memory schemes for fast packet buffersGARCIA, Jorge; MARCH, Maribel; CERDA, Llorenc et al.Workshop on high performance switching and routing. 2004, pp 15-19, isbn 0-7803-8375-3, 1Vol, 5 p.Conference Paper

Per-bit sense amplifier scheme for 1GHz SRAM macro in sub-100nm CMOS technologyTAKEDA, K; HAGIHARA, Y; AIMOTO, Y et al.IEEE International Solid-State Circuits Conference. 2004, pp 502-503, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 4Gb/s/pin 4-level simultaneous bidirectional 10 using a 500MHz clock for high-speed memoryKIM, Jin-Hyun; KIM, Su-A; KIM, Woo-Seop et al.IEEE International Solid-State Circuits Conference. 2004, pp 248-249, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAMKIKUCHI, T; MORIYA, S; NAKATSUKA, Y et al.International Electron Devices Meeting. 2004, pp 923-926, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

An alpha immune and ultra low neutron SER high density SRAMROCHE, Philippe; JACQUET, Francois; CAILLAT, Christian et al.IEEE international reliability physics symposium. 2004, pp 671-672, isbn 0-7803-8315-X, 1Vol, 2 p.Conference Paper

The effectiveness of scan test and its new variantsVAN DE GOOR, Ad J; HAMDIOUI, Said; AL-ARS, Zaid et al.IEEE International Workshop on Memory Technology, Design and Testing. 2004, pp 26-31, isbn 0-7695-2193-2, 1Vol, 6 p.Conference Paper

Statistical approach to design DRAM bitcell considering overlay errorsPYO, Yu-Jin; KIM, Dae-Wook; PARK, Jai-Kyun et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7275, issn 0277-786X, isbn 978-0-8194-7528-2 0-8194-7528-9, 1Vol, 72751L.1-72751L.7Conference Paper

Comparison between neutron-induced system-SER and accelerated-SER in SRAMsKOBAYASHI, Hajime; USUKI, Hideki; SHIRAISHI, Ken et al.IEEE international reliability physics symposium. 2004, pp 288-293, isbn 0-7803-8315-X, 1Vol, 6 p.Conference Paper