Low-temperature operation of silicon dynamic random-access memoriesWYNS, P; ANDERSON, R. L.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 8, pp 1423-1428, issn 0018-9383, 6 p.Article

A 128K×8 70-MHz multiport video RAM with auto register reload and 8×4 block WRITE featurePINKHAM, R; RUSSELL, D; GUILLEMAUD, A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1133-1139, issn 0018-9200Article

A 32K ASIC synchronous RAM using a two-transistor basic cellYUEN, A; TSAO, P; YIN, P et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 57-61, issn 0018-9200, 5 p.Article

A 14-ns 1-Mbit CMOS SRAM with variable bit organizationKOHNO, Y; WADA, T; ANAMI, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1060-1066, issn 0018-9200Article

A 25-ns low-power full-CMOS 1-Mbit (128K×8) SRAMCHU, S. T; DIKKEN, J; HARTGRING, C. D et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1078-1084, issn 0018-9200Article

Charle losses of N-doped trench cellsRISCH, L; MALY, R; BERGNER, W et al.Japanese journal of applied physics. 1988, Vol 27, Num 11, pp L2223-L2226, issn 0021-4922, part 2Article

Contribution à l'étude du test aléatoire de mémoires RAM = Study of the random test of RAM memoryFUENTES, Antoine; DAVID, René.1986, 110 pThesis

Optoelectronic dynamic random access memory cell utilizing a three-terminal N-channel self-aligned double-heterostructure optoelectronic switchTAYLOR, G. W; CRAWFORD, D. L; SIMMONS, J. G et al.Applied physics letters. 1989, Vol 54, Num 6, pp 543-545, issn 0003-6951, 3 p.Article

A 12-ns ECL I/O 256K×1-bit SRAM using a 1-υm BiCMOS technologyKERTIS, R. A; SMITH, D. D; BOWMAN, T. L et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1048-1053, issn 0018-9200Article

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAMHORIGUCHI, M; AOKI, M; TANAKA, H et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1128-1132, issn 0018-9200Article

Soft error rates in 64 K and 256 K DRAMsHAQUE, A. K. M. M; YATES, J; STEVENS, D et al.Electronics Letters. 1986, Vol 22, Num 22, pp 1188-1189, issn 0013-5194Article

Comment on the spreading dynamics of a liquid drop on a viscoelastic solidHILLS, D. A; SACKFIELD, A.Journal of physics. D, Applied physics (Print). 1989, Vol 22, Num 2, pp 371-372, issn 0022-3727, 2 p.Article

A 15-ns 1-Mbit CMOS SRAMSASAKI, K; HANAMURA, S; TOYOSHIMA, H et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1067-1072, issn 0018-9200Article

An experimental 1-Mbit CMOS SRAM with configurable organization and operationWILLIAMS, T; BEILSTEIN, K; ROBERGE, M et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1085-1094, issn 0018-9200Article

An optically delineated 4.2-μm² self-aligned isolated-plate stacked-capacitor DRAM cellKIMURA, S.-I; KAWAMOTO, Y; HASEGAWA, N et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 10, pp 1591-1595, issn 0018-9383Article

The impact of data-line interference noise on DRAM scalingNAKAGOME, Y; AOKI, M; IKENAGA, S et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1120-1127, issn 0018-9200Article

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architectureINOUE, M; YAMADA, T; AOI, N et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1104-1112, issn 0018-9200Article

A 20-ns 128-kbit×4 high-speed DRAM with 330-Mbit/s data rateLU, N. C. C; CHAO, H. H; WEI HWANG et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1140-1149, issn 0018-9200Article

A 60-ns 16-Mbit CMOS DRAM with a transposed date-line structureAOKI, M; NAKAGOME, Y; ITOH, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1113-1119, issn 0018-9200Article

FeRAM technology: Today and futureKUNISHIMA, Iwao; NAGEL, Nicolas.Proceedings - Electrochemical Society. 2003, pp 149-151, issn 0161-6374, isbn 1-56677-376-8, 3 p.Conference Paper

A 7.5-ns 32K×8 CMOS SRAMOKUYAMA, H; NAKANO, T; NISHIDA, S et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1054-1059, issn 0018-9200Article

An 18-ns 1-Mbit CMOS SRAMSHIMADA, H; TANGE, Y; TANIMOTO, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1073-1077, issn 0018-9200Article

Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabricationOHKURA, M; KUSUKAWA, K; SUNAMI, H et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 2, pp 333-339, issn 0018-9383, 7 p.Article

A 4-ns 4K×1-bit two-port BiCMOS SRAMTSEN-SHAU YANG; HOROWITZ, M. A; WOOLEY, B. A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1030-1040, issn 0018-9200Article

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devicesWONG, D. T; ADAMS, R. D; ARUP BHATTACHARYYA et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1095-1103, issn 0018-9200Article