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Circuits for CMOS high-speed I/O in sub-100 nm technologies : VLSI design technology in the sub-100 nm eraTAMURA, Hirotaka; KIBUNE, Masaya; YAMAGUCHI, Hisakatsu et al.IEICE transactions on electronics. 2006, Vol 89, Num 3, pp 300-313, issn 0916-8524, 14 p.Article
