24512437
Results 1 to 1 of 1
Selection :
Relationship between settling time and pole-zero placements for three-stage CMOS opampCHANDRAWAT, Uday Bhanu Singh; MISHRA, D. K.International journal of electronics. 2011, Vol 98, Num 7-9, pp 901-922, issn 0020-7217, 22 p.Article
