Accelerated image processing on FPGAs
- Author
- DRAPER, Bruce A1 ; BEVERIDGE, J. Ross1 ; BÖHM, A. P1 ; ROSS, Charles1 ; CHAWATHE, Monica1
[1] Department of Computer Science, Colorado State University, Fort Collins, CO 80523, United States - Source
IEEE transactions on image processing. 2003, Vol 12, Num 12, pp 1543-1551, 9 p ; ref : 30 ref
- ISSN
- 1057-7149
- Scientific domain
- Telecommunications
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Compilateur Réseau porte programmable Traitement image Traitement signal vidéo
- Keyword (en)
- Compiler Field programmable gate array Image processing Video signal processing
- Keyword (es)
- Compilador Red puerta programable Procesamiento imagen
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D04 Telecommunications and information theory / 001D04A Information, signal and communications theory / 001D04A05 Signal processing / 001D04A05C Image processing
- Discipline
- Electronics Telecommunications and information theory
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 15408633
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Access to the document
Install on your browser
DOI
10.1109/TIP.2003.819226 
https://dx.doi.org/10.1109/TIP.2003.819226
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TIP.2003.819226\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:37:\"Accelerated image processing on FPGAs\";s:9:\"\u0000*\u0000jtitle\";s:37:\"IEEE transactions on image processing\";s:9:\"\u0000*\u0000stitle\";s:25:\"IEEE trans. image process\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:2:\"12\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1543\";s:8:\"\u0000*\u0000epage\";s:4:\"1551\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1057-7149\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"DRAPER\";s:10:\"\u0000*\u0000aufirst\";s:7:\"Bruce A\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:4:{i:0;s:18:\"BEVERIDGE, J. Ross\";i:1;s:11:\"B\u00d6HM, A. P\";i:2;s:13:\"ROSS, Charles\";i:3;s:16:\"CHAWATHE, Monica\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:37:\"Accelerated image processing on FPGAs\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"9\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TIP.2003.819226\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:37:\"Accelerated image processing on FPGAs\";s:9:\"\u0000*\u0000jtitle\";s:37:\"IEEE transactions on image processing\";s:9:\"\u0000*\u0000stitle\";s:25:\"IEEE trans. image process\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:2:\"12\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1543\";s:8:\"\u0000*\u0000epage\";s:4:\"1551\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1057-7149\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"DRAPER\";s:10:\"\u0000*\u0000aufirst\";s:7:\"Bruce A\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:4:{i:0;s:18:\"BEVERIDGE, J. Ross\";i:1;s:11:\"B\u00d6HM, A. P\";i:2;s:13:\"ROSS, Charles\";i:3;s:16:\"CHAWATHE, Monica\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:37:\"Accelerated image processing on FPGAs\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"9\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"UnpaywallOpenUrl\":35:{s:8:\"\u0000*\u0000email\";s:27:\"assistance-portail@inist.fr\";s:6:\"\u0000*\u0000fmt\";N;s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TIP.2003.819226\";s:6:\"\u0000*\u0000pii\";N;s:7:\"\u0000*\u0000pmid\";N;s:9:\"\u0000*\u0000atitle\";N;s:9:\"\u0000*\u0000jtitle\";N;s:9:\"\u0000*\u0000stitle\";N;s:7:\"\u0000*\u0000date\";N;s:9:\"\u0000*\u0000volume\";N;s:8:\"\u0000*\u0000issue\";N;s:8:\"\u0000*\u0000spage\";N;s:8:\"\u0000*\u0000epage\";N;s:8:\"\u0000*\u0000pages\";N;s:7:\"\u0000*\u0000issn\";N;s:8:\"\u0000*\u0000eissn\";N;s:9:\"\u0000*\u0000aulast\";N;s:10:\"\u0000*\u0000aufirst\";N;s:9:\"\u0000*\u0000auinit\";N;s:10:\"\u0000*\u0000auinitm\";N;s:5:\"\u0000*\u0000au\";N;s:9:\"\u0000*\u0000aucorp\";N;s:7:\"\u0000*\u0000isbn\";N;s:8:\"\u0000*\u0000coden\";N;s:8:\"\u0000*\u0000genre\";N;s:7:\"\u0000*\u0000part\";N;s:9:\"\u0000*\u0000btitle\";N;s:8:\"\u0000*\u0000title\";N;s:8:\"\u0000*\u0000place\";N;s:6:\"\u0000*\u0000pub\";N;s:10:\"\u0000*\u0000edition\";N;s:9:\"\u0000*\u0000tpages\";N;s:9:\"\u0000*\u0000series\";N;s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";N;}"
Unpaywall access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TIP.2003.819226\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:37:\"Accelerated image processing on FPGAs\";s:9:\"\u0000*\u0000jtitle\";s:37:\"IEEE transactions on image processing\";s:9:\"\u0000*\u0000stitle\";s:25:\"IEEE trans. image process\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:2:\"12\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1543\";s:8:\"\u0000*\u0000epage\";s:4:\"1551\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1057-7149\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"DRAPER\";s:10:\"\u0000*\u0000aufirst\";s:7:\"Bruce A\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:4:{i:0;s:18:\"BEVERIDGE, J. Ross\";i:1;s:11:\"B\u00d6HM, A. P\";i:2;s:13:\"ROSS, Charles\";i:3;s:16:\"CHAWATHE, Monica\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:37:\"Accelerated image processing on FPGAs\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"9\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TIP.2003.819226\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:37:\"Accelerated image processing on FPGAs\";s:9:\"\u0000*\u0000jtitle\";s:37:\"IEEE transactions on image processing\";s:9:\"\u0000*\u0000stitle\";s:25:\"IEEE trans. image process\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:2:\"12\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1543\";s:8:\"\u0000*\u0000epage\";s:4:\"1551\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1057-7149\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"DRAPER\";s:10:\"\u0000*\u0000aufirst\";s:7:\"Bruce A\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:4:{i:0;s:18:\"BEVERIDGE, J. Ross\";i:1;s:11:\"B\u00d6HM, A. P\";i:2;s:13:\"ROSS, Charles\";i:3;s:16:\"CHAWATHE, Monica\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:37:\"Accelerated image processing on FPGAs\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"9\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
arXiv access
