Exploiting redundancy to speedup reconfiguration of an FPGA
- Autor
- KENNEDY, Irwin1
[1] Division of Informatics, University of Edinburgh, Mayfield Road, Edinburgh EH9 3JZ, United Kingdom - Titulo de la conferencia
- FPL 2003 : field-programmable logic and applications (Lisbon, 1-3 September 2003)
- Nombre de la conferencia
- International conference on field-programmable logic and applications (13 ; Lisbon 2003-09-01)
- Autor ( monografía)
- Cheung, Peter Y.K (Editor); Constantinides, George A (Editor); de Sousa, Jose T (Editor)
- Fuente
Lecture notes in computer science. 2003, pp 262-271, 10 p ; ref : 6 ref
- ISSN
- 0302-9743
- ISBN
- 3-540-40822-3
- Campo Científico
- Computer science
- Editor
- Springer, Berlin
- País de la publicación
- Germany
- Tipo de documento
- Conference Paper
- Idioma
- English
- Palabra clave (fr)
- Architecture reconfigurable Conception circuit Haute performance Puissance faible Reconfiguration Réseau porte programmable
- Palabra clave (in)
- Reconfigurable architectures Circuit design High performance Low power Reconfiguration Field programmable gate array
- Palabra clave (es)
- Diseño circuito Alto rendimiento Potencia débil Reconfiguración Red puerta programable
- Clasificación
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Disciplina
- Electronics
- Procedencia
- Inist-CNRS
- Base de datos
- PASCAL
- Identificador INIST
- 15509333
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1007/978-3-540-45234-8_26 
https://dx.doi.org/10.1007/978-3-540-45234-8_26
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:28:\"10.1007\/978-3-540-45234-8_26\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:9:\"\u0000*\u0000jtitle\";s:33:\"Lecture notes in computer science\";s:9:\"\u0000*\u0000stitle\";s:23:\"Lect. notes comput. sci\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"262\";s:8:\"\u0000*\u0000epage\";s:3:\"271\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0302-9743\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"KENNEDY\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Irwin\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"3-540-40822-3\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:81:\"FPL 2003 : field-programmable logic and applications (Lisbon, 1-3 September 2003)\";s:8:\"\u0000*\u0000title\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:8:\"\u0000*\u0000place\";s:6:\"Berlin\";s:6:\"\u0000*\u0000pub\";s:8:\"Springer\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Acceso mediante Panist
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:28:\"10.1007\/978-3-540-45234-8_26\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:9:\"\u0000*\u0000jtitle\";s:33:\"Lecture notes in computer science\";s:9:\"\u0000*\u0000stitle\";s:23:\"Lect. notes comput. sci\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"262\";s:8:\"\u0000*\u0000epage\";s:3:\"271\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0302-9743\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"KENNEDY\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Irwin\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"3-540-40822-3\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:81:\"FPL 2003 : field-programmable logic and applications (Lisbon, 1-3 September 2003)\";s:8:\"\u0000*\u0000title\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:8:\"\u0000*\u0000place\";s:6:\"Berlin\";s:6:\"\u0000*\u0000pub\";s:8:\"Springer\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Acceso mediante Istex
"O:16:\"UnpaywallOpenUrl\":35:{s:8:\"\u0000*\u0000email\";s:27:\"assistance-portail@inist.fr\";s:6:\"\u0000*\u0000fmt\";N;s:6:\"\u0000*\u0000doi\";s:28:\"10.1007\/978-3-540-45234-8_26\";s:6:\"\u0000*\u0000pii\";N;s:7:\"\u0000*\u0000pmid\";N;s:9:\"\u0000*\u0000atitle\";N;s:9:\"\u0000*\u0000jtitle\";N;s:9:\"\u0000*\u0000stitle\";N;s:7:\"\u0000*\u0000date\";N;s:9:\"\u0000*\u0000volume\";N;s:8:\"\u0000*\u0000issue\";N;s:8:\"\u0000*\u0000spage\";N;s:8:\"\u0000*\u0000epage\";N;s:8:\"\u0000*\u0000pages\";N;s:7:\"\u0000*\u0000issn\";N;s:8:\"\u0000*\u0000eissn\";N;s:9:\"\u0000*\u0000aulast\";N;s:10:\"\u0000*\u0000aufirst\";N;s:9:\"\u0000*\u0000auinit\";N;s:10:\"\u0000*\u0000auinitm\";N;s:5:\"\u0000*\u0000au\";N;s:9:\"\u0000*\u0000aucorp\";N;s:7:\"\u0000*\u0000isbn\";N;s:8:\"\u0000*\u0000coden\";N;s:8:\"\u0000*\u0000genre\";N;s:7:\"\u0000*\u0000part\";N;s:9:\"\u0000*\u0000btitle\";N;s:8:\"\u0000*\u0000title\";N;s:8:\"\u0000*\u0000place\";N;s:6:\"\u0000*\u0000pub\";N;s:10:\"\u0000*\u0000edition\";N;s:9:\"\u0000*\u0000tpages\";N;s:9:\"\u0000*\u0000series\";N;s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";N;}"
Acceso mediante Unpaywall
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:28:\"10.1007\/978-3-540-45234-8_26\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:9:\"\u0000*\u0000jtitle\";s:33:\"Lecture notes in computer science\";s:9:\"\u0000*\u0000stitle\";s:23:\"Lect. notes comput. sci\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"262\";s:8:\"\u0000*\u0000epage\";s:3:\"271\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0302-9743\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"KENNEDY\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Irwin\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"3-540-40822-3\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:81:\"FPL 2003 : field-programmable logic and applications (Lisbon, 1-3 September 2003)\";s:8:\"\u0000*\u0000title\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:8:\"\u0000*\u0000place\";s:6:\"Berlin\";s:6:\"\u0000*\u0000pub\";s:8:\"Springer\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Acceso mediante Europe PubMed Central
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:28:\"10.1007\/978-3-540-45234-8_26\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:9:\"\u0000*\u0000jtitle\";s:33:\"Lecture notes in computer science\";s:9:\"\u0000*\u0000stitle\";s:23:\"Lect. notes comput. sci\";s:7:\"\u0000*\u0000date\";s:4:\"2003\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"262\";s:8:\"\u0000*\u0000epage\";s:3:\"271\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0302-9743\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"KENNEDY\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Irwin\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"3-540-40822-3\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:81:\"FPL 2003 : field-programmable logic and applications (Lisbon, 1-3 September 2003)\";s:8:\"\u0000*\u0000title\";s:59:\"Exploiting redundancy to speedup reconfiguration of an FPGA\";s:8:\"\u0000*\u0000place\";s:6:\"Berlin\";s:6:\"\u0000*\u0000pub\";s:8:\"Springer\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:2:\"10\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Acceso mediante arXiv
