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Approach to partially self-checking combinational circuits design

Author
DJORDJEVIC, Goran Lj1 ; STOJCEV, Mile K1 ; STANKOVIC, Tatjana R1
[1] Faculty of Electronic Engineering, University of Nis, Beogradska 14, 18000 Nis, Serbia and Montenegro, Yugoslavia
Source

Microelectronics journal. 2004, Vol 35, Num 12, pp 945-952, 8 p ; ref : 18 ref

ISSN
0959-8324
Scientific domain
Electronics
Publisher
Elsevier Science, Oxford
Publication country
United Kingdom
Document type
Article
Language
English
Author keyword
Approximation of logic functions Concurrent error detection Fault tolerance Partially self-checking circuits
Keyword (fr)
Autotest Circuit combinatoire Circuit comparateur Conception circuit Détection erreur Etude comparative Evaluation performance Fonction logique Méthode heuristique Tolérance faute
Keyword (en)
Built in self test Combinatory circuit Comparator circuit Circuit design Error detection Comparative study Performance evaluation Logical function Heuristic method Fault tolerance
Keyword (es)
Autoprueba Circuito combinatorio Circuito comparador Diseño circuito Detección error Estudio comparativo Evaluación prestación Función lógica Método heurístico Tolerancia falta
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03B Testing, measurement, noise and reliability

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
16270096

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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