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Multiobjective optimization of VLSI interconnect parameters

Author
ANAND, M. B1 ; SHIBATA, H1 ; KAKUMU, M2
[1] ULSI Process Engineering Laboratory, Advanced Microelectronics Center, Toshiba Corp., Yokohama 235, Japan
[2] Microprocessor Product Engineering Department, Micro & Custom LSI Division, Toshiba Corp., Kawasaki 210, Japan
Source

IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 12, pp 1252-1261 ; ref : 17 ref

CODEN
ITCSDI
ISSN
0278-0070
Scientific domain
Electronics
Publisher
Institute of Electrical and Electronics Engineers, New York, NY
Publication country
United States
Document type
Article
Language
English
Keyword (fr)
Chemin critique Circuit VLSI Circuit intégré Conception assistée Interconnexion Modélisation Optimisation Programmation non linéaire Puce électronique Optimisation multiobjectif
Keyword (en)
Critical path VLSI circuit Integrated circuit Computer aided design Interconnection Modeling Optimization Non linear programming Chip Multiobjective optimization
Keyword (es)
Recorrido crítico Circuito VLSI Circuito integrado Concepción asistida Interconexión Modelización Optimización Programación no lineal Pulga electrónica
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
1641958

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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