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Copper electrodeposition of high-aspect-ratio vias for three dimensional packaging

Author
KONDO, Kazuo1 ; YONEZAWA, Toshihiro1 ; TOMISAKA, Manabu2 ; YONEMURA, Hitoshi2 ; HOSHINO, Masataka2 ; TAGUCHI, Yuichi1 ; TAKAHASHI, Kenji2
[1] Department of Applied Chemistry, Okayama University, 3-1-1, Tsushima-naka, Okayama, Okayama, 700-0082, Japan
[2] Tsukuba Research Center, Electronic System Integration Technology Research, Department, ASET Room C-B-5, Tsukuba Center Inc., Sengen 2-1-6, Tsukuba, Ibaraki, 305-0047, Japan
Conference title
Copper interconnects, new contact metallurgies/structures, and low-k interlevel dielectrics II (Orlando FL, 12-17 October 2003)
Conference name
Copper interconnects, new contact metallurgies/structures, and low-k interlevel dielectrics (2 ; Orlando FL 2003-10-12)
Author (monograph)
Mathad, G.S (Editor); Rathore, H.S (Editor); Konda, K (Editor); Reidsema-Simpson, C (Editor)
Electrochemical Society, Electronics Division, Pennington NJ, United States (Organiser of meeting)
Source

Proceedings - Electrochemical Society. 2003, pp 28-32, 5 p ; ref : 5 ref

ISSN
0161-6374
ISBN
1-56677-390-3
Scientific domain
General chemistry, physical chemistry; Crystallography; Electronics; Electrical engineering; Energy; Physics
Publisher
Electrochemical Society, Pennington NJ
Publication country
United States
Document type
Conference Paper
Language
English
Keyword (fr)
Circuit intégré Densité courant Déphaseur Dépôt électrolytique Fabrication microélectronique Interconnexion Modèle 3 dimensions Méthode à pas Optimisation Packaging électronique Rapport aspect Retard signal Trou interconnexion
Keyword (en)
Integrated circuit Current density Phase shifter Electrodeposition Microelectronic fabrication Interconnection Three dimensional model Step method Optimization Electronic packaging Aspect ratio Signal delay Via hole
Keyword (es)
Circuito integrado Densidad corriente Desfasador Depósito electrolítico Fabricación microeléctrica Interconexión Modelo 3 dimensiones Método a paso Optimización Packaging electrónico Relación dimensional Retardo señal Agujero interconexión
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing

Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F17 Microelectronic fabrication (materials and surfaces technology)

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
16524034

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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