Full-chip lithography simulation and design analvsis : How OPC is changing IC design
- Author
- SPENCE, Chris1
[1] Advanced Micro Devices, 1 AMD Place, Sunnyvale, CA 94088-3453, United States - Conference title
- Design and process integration for microelectronic manufacturing III (San Jose CA, 3-4 March 2005)
- Conference name
- Design and process integration for microelectronic manufacturing. Conference (3 ; San Jose CA 2005-03-03)
- Author (monograph)
- Liebmann, Lars W (Editor)
International Society for Optical Engineering, Bellingham WA, United States (Organiser of meeting) - Source
SPIE proceedings series. 2005, pp xi-xxiv ; ref : 30 ref
- ISBN
- 0-8194-5736-1
- Scientific domain
- Electronics; Optics; Physics; Telecommunications
- Publisher
- SPIE, Bellingham WA
- Publication country
- International
- Document type
- Conference Paper
- Language
- English
- Keyword (fr)
- Article synthèse Automatisation conception électronique Conception circuit intégré Effet proximité(lithographie) Fabrication microélectronique Implantation circuit Photolithographie Procédé fabrication Simulation système
- Keyword (en)
- Review Electronic design automation Integrated circuit design Proximity effect (lithography) Microelectronic fabrication Circuit layout Photolithography Manufacturing process System simulation
- Keyword (es)
- Artículo síntesis Fabricación microeléctrica Fotolitografía Procedimiento fabricación Simulación sistema
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F17 Microelectronic fabrication (materials and surfaces technology)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 17199366
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Install on your browser
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:9:\"\u0000*\u0000jtitle\";s:23:\"SPIE proceedings series\";s:9:\"\u0000*\u0000stitle\";s:14:\"SPIE proc. ser\";s:7:\"\u0000*\u0000date\";s:4:\"2005\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:2:\"xi\";s:8:\"\u0000*\u0000epage\";s:4:\"xxiv\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"SPENCE\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Chris\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-8194-5736-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:98:\"Design and process integration for microelectronic manufacturing III (San Jose CA, 3-4 March 2005)\";s:8:\"\u0000*\u0000title\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:8:\"\u0000*\u0000place\";s:13:\"Bellingham WA\";s:6:\"\u0000*\u0000pub\";s:4:\"SPIE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:9:\"\u0000*\u0000jtitle\";s:23:\"SPIE proceedings series\";s:9:\"\u0000*\u0000stitle\";s:14:\"SPIE proc. ser\";s:7:\"\u0000*\u0000date\";s:4:\"2005\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:2:\"xi\";s:8:\"\u0000*\u0000epage\";s:4:\"xxiv\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"SPENCE\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Chris\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-8194-5736-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:98:\"Design and process integration for microelectronic manufacturing III (San Jose CA, 3-4 March 2005)\";s:8:\"\u0000*\u0000title\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:8:\"\u0000*\u0000place\";s:13:\"Bellingham WA\";s:6:\"\u0000*\u0000pub\";s:4:\"SPIE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:9:\"\u0000*\u0000jtitle\";s:23:\"SPIE proceedings series\";s:9:\"\u0000*\u0000stitle\";s:14:\"SPIE proc. ser\";s:7:\"\u0000*\u0000date\";s:4:\"2005\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:2:\"xi\";s:8:\"\u0000*\u0000epage\";s:4:\"xxiv\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"SPENCE\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Chris\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-8194-5736-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:98:\"Design and process integration for microelectronic manufacturing III (San Jose CA, 3-4 March 2005)\";s:8:\"\u0000*\u0000title\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:8:\"\u0000*\u0000place\";s:13:\"Bellingham WA\";s:6:\"\u0000*\u0000pub\";s:4:\"SPIE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:9:\"\u0000*\u0000jtitle\";s:23:\"SPIE proceedings series\";s:9:\"\u0000*\u0000stitle\";s:14:\"SPIE proc. ser\";s:7:\"\u0000*\u0000date\";s:4:\"2005\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:2:\"xi\";s:8:\"\u0000*\u0000epage\";s:4:\"xxiv\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"SPENCE\";s:10:\"\u0000*\u0000aufirst\";s:5:\"Chris\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-8194-5736-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:98:\"Design and process integration for microelectronic manufacturing III (San Jose CA, 3-4 March 2005)\";s:8:\"\u0000*\u0000title\";s:84:\"Full-chip lithography simulation and design analvsis : How OPC is changing IC design\";s:8:\"\u0000*\u0000place\";s:13:\"Bellingham WA\";s:6:\"\u0000*\u0000pub\";s:4:\"SPIE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
arXiv access
