A reduced complexity decoder architecture via layered decoding of LDPC codes
- Author
- HOCEVAR, Dale E1
[1] DSP Solutions R&D Center Texas Instruments, Dallas, TX, United States - Conference title
- 2004 IEEE workshop on signal processing systems design and implementation (Proceedings)
- Conference name
- IEEE workshop on signal processing systems design and implementation (Austin TX 2004-10-13)
- Author (monograph)
- IEEE Circuits and systems society, United States (Organiser of meeting)
Signal processing society, United States (Organiser of meeting)
Institute of electrical and electronics engineers, United States (Organiser of meeting) - Source
2004 IEEE workshop on signal processing systems design and implementation (Proceedings). 2004 ; 1Vol, pp 107-112, 6 p ; ref : 19 ref
- ISBN
- 0-7803-8504-7
- Scientific domain
- Telecommunications
- Publisher
- IEEE, Piscataway NJ
- Publication country
- United States
- Document type
- Conference Paper
- Language
- English
- Keyword (fr)
- Architecture système Code contrôle parité Décodage Traitement signal Propagation croyance
- Keyword (en)
- System architecture Parity check codes Decoding Signal processing
- Keyword (es)
- Arquitectura sistema Desciframiento Procesamiento señal
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D04 Telecommunications and information theory / 001D04A Information, signal and communications theory / 001D04A04 Signal and communications theory / 001D04A04B Coding, codes
- Discipline
- Telecommunications and information theory
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 17526326
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Install on your browser
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"107\";s:8:\"\u0000*\u0000epage\";s:3:\"112\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"HOCEVAR\";s:10:\"\u0000*\u0000aufirst\";s:6:\"Dale E\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8504-7\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:87:\"2004 IEEE workshop on signal processing systems design and implementation (Proceedings)\";s:8:\"\u0000*\u0000title\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"6\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"107\";s:8:\"\u0000*\u0000epage\";s:3:\"112\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"HOCEVAR\";s:10:\"\u0000*\u0000aufirst\";s:6:\"Dale E\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8504-7\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:87:\"2004 IEEE workshop on signal processing systems design and implementation (Proceedings)\";s:8:\"\u0000*\u0000title\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"6\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"107\";s:8:\"\u0000*\u0000epage\";s:3:\"112\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"HOCEVAR\";s:10:\"\u0000*\u0000aufirst\";s:6:\"Dale E\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8504-7\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:87:\"2004 IEEE workshop on signal processing systems design and implementation (Proceedings)\";s:8:\"\u0000*\u0000title\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"6\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"107\";s:8:\"\u0000*\u0000epage\";s:3:\"112\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:7:\"HOCEVAR\";s:10:\"\u0000*\u0000aufirst\";s:6:\"Dale E\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:0:{}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8504-7\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:87:\"2004 IEEE workshop on signal processing systems design and implementation (Proceedings)\";s:8:\"\u0000*\u0000title\";s:76:\"A reduced complexity decoder architecture via layered decoding of LDPC codes\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"6\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
arXiv access
