VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning
- Author
- MICHEL, J1 ; HERVE, Y2
[1] LEPSI, Université Louis Pasteur, Strasbourg, France
[2] CNRS/PHASE, Université Louis Pasteur, Strasbourg, France - Conference title
- IEEE-ISIE 2004 (proceedings of the 2004 IEEE International Symposium on Industrial Electronics, Ajaccio, France, May 4-7, 2004)
- Conference name
- International symposium on industrial electronics (Ajaccio 2004-05-04)
- Author (monograph)
- Institute of electrical and electronics engineers, United States (Organiser of meeting)
- Source
IEEE-ISIE 2004 (proceedings of the 2004 IEEE International Symposium on Industrial Electronics, Ajaccio, France, May 4-7, 2004). 2004 ; 2Vol ; Vol1, 211-216 ; ref : 17 ref
- ISBN
- 0-7803-8304-4
- Scientific domain
- Control theory, operational research; Electronics; Electrical engineering; Computer science
- Publisher
- IEEE, Piscataway NJ
- Publication country
- United States
- Document type
- Conference Paper
- Language
- English
- Keyword (fr)
- Algorithme apprentissage Algorithme parallèle Analyse comportementale Apprentissage Classification Composant électrique Etude comparative Evaluation performance Langage VHDL Logiciel MATLAB Mode courant Puce électronique Robustesse Réseau neuronal Simulation électrique
- Keyword (en)
- Learning algorithm Parallel algorithm Behavioral analysis Learning Classification Electrical component Comparative study Performance evaluation VHDL language MATLAB software Current mode Chip Robustness Neural network Electrical simulation
- Keyword (es)
- Algoritmo aprendizaje Algoritmo paralelo Análisis conductual Aprendizaje Clasificación Componente eléctrico Estudio comparativo Evaluación prestación Lenguaje VHDL Programa MATLAB Modo corriente Pulga electrónica Robustez Red neuronal Simulación eléctrica
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G03 Neural networks
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 17546076
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:0:\"\";s:8:\"\u0000*\u0000epage\";s:0:\"\";s:8:\"\u0000*\u0000pages\";s:13:\"Vol1, 211-216\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"MICHEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"J\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:8:\"HERVE, Y\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8304-4\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:127:\"IEEE-ISIE 2004 (proceedings of the 2004 IEEE International Symposium on Industrial Electronics, Ajaccio, France, May 4-7, 2004)\";s:8:\"\u0000*\u0000title\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:0:\"\";s:8:\"\u0000*\u0000epage\";s:0:\"\";s:8:\"\u0000*\u0000pages\";s:13:\"Vol1, 211-216\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"MICHEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"J\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:8:\"HERVE, Y\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8304-4\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:127:\"IEEE-ISIE 2004 (proceedings of the 2004 IEEE International Symposium on Industrial Electronics, Ajaccio, France, May 4-7, 2004)\";s:8:\"\u0000*\u0000title\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:0:\"\";s:8:\"\u0000*\u0000epage\";s:0:\"\";s:8:\"\u0000*\u0000pages\";s:13:\"Vol1, 211-216\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"MICHEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"J\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:8:\"HERVE, Y\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8304-4\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:127:\"IEEE-ISIE 2004 (proceedings of the 2004 IEEE International Symposium on Industrial Electronics, Ajaccio, France, May 4-7, 2004)\";s:8:\"\u0000*\u0000title\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
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"O:11:\"BaseOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:0:\"\";s:8:\"\u0000*\u0000epage\";s:0:\"\";s:8:\"\u0000*\u0000pages\";s:13:\"Vol1, 211-216\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"MICHEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"J\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:8:\"HERVE, Y\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8304-4\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:127:\"IEEE-ISIE 2004 (proceedings of the 2004 IEEE International Symposium on Industrial Electronics, Ajaccio, France, May 4-7, 2004)\";s:8:\"\u0000*\u0000title\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
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"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:0:\"\";s:8:\"\u0000*\u0000epage\";s:0:\"\";s:8:\"\u0000*\u0000pages\";s:13:\"Vol1, 211-216\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:6:\"MICHEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"J\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:8:\"HERVE, Y\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8304-4\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:127:\"IEEE-ISIE 2004 (proceedings of the 2004 IEEE International Symposium on Industrial Electronics, Ajaccio, France, May 4-7, 2004)\";s:8:\"\u0000*\u0000title\";s:145:\"VHDL-AMS behavioral model of an analog neural networks based on a fully parallel weight perturbation algorithm using incremental on-chip learning\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
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