Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate
- Author
- SEONG GEON PARK1 ; BEOM JUN JIN1 ; CHUNG, U.-In1 ; JOO TAE MOON1 ; HYE LAN LEE1 ; HONG BAE PARK1 ; TAEK SOO JEON1 ; CHO, Hag-Ju1 ; SANG YONG KIM1 ; SOO IK JANG1 ; SANG BOM KANG1 ; YU GYUN SHIN1
[1] Process Development Team 2, Semiconductor R&D Center, Samsung Electronics Co. Ltd. San #24 Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyungki-Do 449-711, Korea, Republic of - Conference title
- IEEE International Electron Devices Meeting 2004 (IEDM technical digest)
- Conference name
- International Electron Devices Meeting (San Francisco CA 2004)
- Author (monograph)
- IEEE Electron Devices Society, United States (Organiser of meeting)
- Source
IEEE International Electron Devices Meeting 2004 (IEDM technical digest). 2004 ; 1Vol, pp 515-518, 4 p ; ref : 3 ref
- ISBN
- 0-7803-8684-1
- Scientific domain
- Electronics
- Publisher
- IEEE, Piscataway NJ
- Publication country
- United States
- Document type
- Conference Paper
- Language
- English
- Keyword (fr)
- Canal enterré Canal transistor Circuit intégré Courant fuite Courant grille Endommagement Grille transistor Implémentation Mémoire accès direct dynamique Mémoire accès direct Niveau Fermi Oxyde grille Polycristal Recuit Stabilité thermique Technologie NMOS Technologie PMOS Transistor MOSFET
- Keyword (en)
- Buried channel Transistor channel Integrated circuit Leakage current Gate current Damaging Transistor gate Implementation Dynamic random access memory Random access memory Fermi level Gate oxide Polycrystal Annealing Thermal stability NMOS technology PMOS technology MOSFET
- Keyword (es)
- Canal enterrado Canal transistor Circuito integrado Corriente escape Corriente rejilla Deterioración Rejilla transistor Implementación Memoria acceso directo Nivel Fermi Oxido rejilla Policristal Recocido Estabilidad térmica Tecnología NMOS Tecnología PMOS
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F04 Transistors
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 17806468
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Install on your browser
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"515\";s:8:\"\u0000*\u0000epage\";s:3:\"518\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:15:\"SEONG GEON PARK\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:11:{i:0;s:12:\"BEOM JUN JIN\";i:1;s:12:\"CHUNG, U.-In\";i:2;s:12:\"JOO TAE MOON\";i:3;s:11:\"HYE LAN LEE\";i:4;s:13:\"HONG BAE PARK\";i:5;s:13:\"TAEK SOO JEON\";i:6;s:11:\"CHO, Hag-Ju\";i:7;s:13:\"SANG YONG KIM\";i:8;s:11:\"SOO IK JANG\";i:9;s:13:\"SANG BOM KANG\";i:10;s:12:\"YU GYUN SHIN\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8684-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:72:\"IEEE International Electron Devices Meeting 2004 (IEDM technical digest)\";s:8:\"\u0000*\u0000title\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"4\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"515\";s:8:\"\u0000*\u0000epage\";s:3:\"518\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:15:\"SEONG GEON PARK\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:11:{i:0;s:12:\"BEOM JUN JIN\";i:1;s:12:\"CHUNG, U.-In\";i:2;s:12:\"JOO TAE MOON\";i:3;s:11:\"HYE LAN LEE\";i:4;s:13:\"HONG BAE PARK\";i:5;s:13:\"TAEK SOO JEON\";i:6;s:11:\"CHO, Hag-Ju\";i:7;s:13:\"SANG YONG KIM\";i:8;s:11:\"SOO IK JANG\";i:9;s:13:\"SANG BOM KANG\";i:10;s:12:\"YU GYUN SHIN\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8684-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:72:\"IEEE International Electron Devices Meeting 2004 (IEDM technical digest)\";s:8:\"\u0000*\u0000title\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"4\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"515\";s:8:\"\u0000*\u0000epage\";s:3:\"518\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:15:\"SEONG GEON PARK\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:11:{i:0;s:12:\"BEOM JUN JIN\";i:1;s:12:\"CHUNG, U.-In\";i:2;s:12:\"JOO TAE MOON\";i:3;s:11:\"HYE LAN LEE\";i:4;s:13:\"HONG BAE PARK\";i:5;s:13:\"TAEK SOO JEON\";i:6;s:11:\"CHO, Hag-Ju\";i:7;s:13:\"SANG YONG KIM\";i:8;s:11:\"SOO IK JANG\";i:9;s:13:\"SANG BOM KANG\";i:10;s:12:\"YU GYUN SHIN\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8684-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:72:\"IEEE International Electron Devices Meeting 2004 (IEDM technical digest)\";s:8:\"\u0000*\u0000title\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"4\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:11:\"BaseOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"515\";s:8:\"\u0000*\u0000epage\";s:3:\"518\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:15:\"SEONG GEON PARK\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:11:{i:0;s:12:\"BEOM JUN JIN\";i:1;s:12:\"CHUNG, U.-In\";i:2;s:12:\"JOO TAE MOON\";i:3;s:11:\"HYE LAN LEE\";i:4;s:13:\"HONG BAE PARK\";i:5;s:13:\"TAEK SOO JEON\";i:6;s:11:\"CHO, Hag-Ju\";i:7;s:13:\"SANG YONG KIM\";i:8;s:11:\"SOO IK JANG\";i:9;s:13:\"SANG BOM KANG\";i:10;s:12:\"YU GYUN SHIN\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8684-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:72:\"IEEE International Electron Devices Meeting 2004 (IEDM technical digest)\";s:8:\"\u0000*\u0000title\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"4\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Base Search access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:10:\"proceeding\";s:6:\"\u0000*\u0000doi\";s:0:\"\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:9:\"\u0000*\u0000jtitle\";s:0:\"\";s:9:\"\u0000*\u0000stitle\";s:0:\"\";s:7:\"\u0000*\u0000date\";s:4:\"2004\";s:9:\"\u0000*\u0000volume\";s:0:\"\";s:8:\"\u0000*\u0000issue\";s:0:\"\";s:8:\"\u0000*\u0000spage\";s:3:\"515\";s:8:\"\u0000*\u0000epage\";s:3:\"518\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:0:\"\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:15:\"SEONG GEON PARK\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:11:{i:0;s:12:\"BEOM JUN JIN\";i:1;s:12:\"CHUNG, U.-In\";i:2;s:12:\"JOO TAE MOON\";i:3;s:11:\"HYE LAN LEE\";i:4;s:13:\"HONG BAE PARK\";i:5;s:13:\"TAEK SOO JEON\";i:6;s:11:\"CHO, Hag-Ju\";i:7;s:13:\"SANG YONG KIM\";i:8;s:11:\"SOO IK JANG\";i:9;s:13:\"SANG BOM KANG\";i:10;s:12:\"YU GYUN SHIN\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:13:\"0-7803-8684-1\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:10:\"proceeding\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:72:\"IEEE International Electron Devices Meeting 2004 (IEDM technical digest)\";s:8:\"\u0000*\u0000title\";s:135:\"Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate\";s:8:\"\u0000*\u0000place\";s:13:\"Piscataway NJ\";s:6:\"\u0000*\u0000pub\";s:4:\"IEEE\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"4\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
arXiv access
