Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits
- Author
- TEMEL, T1 2 ; MORGUL, A2 ; AYDIN, N3
[1] Department of Electronic Engineering, Fatih University, 34500, Büyükçekmece-Istanbul, Turkey
[2] Department of Electrical and Electronic Engineering, Bogazici University, 34342, Istanbul, Turkey
[3] Department of Software Engineering, Bahcesehir University, 34349, Besiktas-Istanbul, Turkey - Source
IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 5, pp 489-496, 8 p ; ref : 20 ref
- ISSN
- 1350-2409
- Scientific domain
- Electronics
- Publisher
- Institution of Electrical Engineers, Stevenage
- Publication country
- United Kingdom
- Document type
- Article
- Language
- English
- Keyword (fr)
- Additionneur Algorithme Caractéristique dynamique Circuit arithmétique Circuit binaire Circuit commutation Circuit intégré Circuit logique Circuit mode courant Commutation circuit Conception circuit Désadaptation Evaluation performance Haute performance Implémentation Logique multivalente Mode courant Mode tension Unité arithmétique
- Keyword (en)
- Adder Algorithm Dynamic characteristic Arithmetic circuit Binary circuit Switching circuit Integrated circuit Logic circuit Current-mode circuits Circuit switching Circuit design Mismatching Performance evaluation High performance Implementation Multivalued logic Current mode Voltage mode Arithmetic unit
- Keyword (es)
- Adicionador Algoritmo Característica dinámica Circuito aritmético Circuito binario Circuito conmutación Circuito integrado Circuito lógico Conmutación circuito Diseño circuito Desadaptación Evaluación prestación Alto rendimiento Implementación Lógica multivalente Modo corriente Modo tensión Unidad aritmética
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A6 Digital circuits
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A7 Switching, multiplexing, switched capacity circuits
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 18245942
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1049/ip-cds:20045096 
https://dx.doi.org/10.1049/ip-cds:20045096
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1049\/ip-cds:20045096\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:46:\"IEE proceedings. Circuits, devices and systems\";s:9:\"\u0000*\u0000stitle\";s:32:\"IEE proc., Circuits devices syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:3:\"153\";s:8:\"\u0000*\u0000issue\";s:1:\"5\";s:8:\"\u0000*\u0000spage\";s:3:\"489\";s:8:\"\u0000*\u0000epage\";s:3:\"496\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1350-2409\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"TEMEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"T\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:9:\"MORGUL, A\";i:1;s:8:\"AYDIN, N\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:35:\"Institution of Electrical Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"8\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1049\/ip-cds:20045096\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:46:\"IEE proceedings. Circuits, devices and systems\";s:9:\"\u0000*\u0000stitle\";s:32:\"IEE proc., Circuits devices syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:3:\"153\";s:8:\"\u0000*\u0000issue\";s:1:\"5\";s:8:\"\u0000*\u0000spage\";s:3:\"489\";s:8:\"\u0000*\u0000epage\";s:3:\"496\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1350-2409\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"TEMEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"T\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:9:\"MORGUL, A\";i:1;s:8:\"AYDIN, N\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:35:\"Institution of Electrical Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"8\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"UnpaywallOpenUrl\":35:{s:8:\"\u0000*\u0000email\";s:27:\"assistance-portail@inist.fr\";s:6:\"\u0000*\u0000fmt\";N;s:6:\"\u0000*\u0000doi\";s:23:\"10.1049\/ip-cds:20045096\";s:6:\"\u0000*\u0000pii\";N;s:7:\"\u0000*\u0000pmid\";N;s:9:\"\u0000*\u0000atitle\";N;s:9:\"\u0000*\u0000jtitle\";N;s:9:\"\u0000*\u0000stitle\";N;s:7:\"\u0000*\u0000date\";N;s:9:\"\u0000*\u0000volume\";N;s:8:\"\u0000*\u0000issue\";N;s:8:\"\u0000*\u0000spage\";N;s:8:\"\u0000*\u0000epage\";N;s:8:\"\u0000*\u0000pages\";N;s:7:\"\u0000*\u0000issn\";N;s:8:\"\u0000*\u0000eissn\";N;s:9:\"\u0000*\u0000aulast\";N;s:10:\"\u0000*\u0000aufirst\";N;s:9:\"\u0000*\u0000auinit\";N;s:10:\"\u0000*\u0000auinitm\";N;s:5:\"\u0000*\u0000au\";N;s:9:\"\u0000*\u0000aucorp\";N;s:7:\"\u0000*\u0000isbn\";N;s:8:\"\u0000*\u0000coden\";N;s:8:\"\u0000*\u0000genre\";N;s:7:\"\u0000*\u0000part\";N;s:9:\"\u0000*\u0000btitle\";N;s:8:\"\u0000*\u0000title\";N;s:8:\"\u0000*\u0000place\";N;s:6:\"\u0000*\u0000pub\";N;s:10:\"\u0000*\u0000edition\";N;s:9:\"\u0000*\u0000tpages\";N;s:9:\"\u0000*\u0000series\";N;s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";N;}"
Unpaywall access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1049\/ip-cds:20045096\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:46:\"IEE proceedings. Circuits, devices and systems\";s:9:\"\u0000*\u0000stitle\";s:32:\"IEE proc., Circuits devices syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:3:\"153\";s:8:\"\u0000*\u0000issue\";s:1:\"5\";s:8:\"\u0000*\u0000spage\";s:3:\"489\";s:8:\"\u0000*\u0000epage\";s:3:\"496\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1350-2409\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"TEMEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"T\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:9:\"MORGUL, A\";i:1;s:8:\"AYDIN, N\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:35:\"Institution of Electrical Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"8\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:11:\"BaseOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1049\/ip-cds:20045096\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:46:\"IEE proceedings. Circuits, devices and systems\";s:9:\"\u0000*\u0000stitle\";s:32:\"IEE proc., Circuits devices syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:3:\"153\";s:8:\"\u0000*\u0000issue\";s:1:\"5\";s:8:\"\u0000*\u0000spage\";s:3:\"489\";s:8:\"\u0000*\u0000epage\";s:3:\"496\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1350-2409\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"TEMEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"T\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:9:\"MORGUL, A\";i:1;s:8:\"AYDIN, N\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:35:\"Institution of Electrical Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"8\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Base Search access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1049\/ip-cds:20045096\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:46:\"IEE proceedings. Circuits, devices and systems\";s:9:\"\u0000*\u0000stitle\";s:32:\"IEE proc., Circuits devices syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:3:\"153\";s:8:\"\u0000*\u0000issue\";s:1:\"5\";s:8:\"\u0000*\u0000spage\";s:3:\"489\";s:8:\"\u0000*\u0000epage\";s:3:\"496\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1350-2409\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"TEMEL\";s:10:\"\u0000*\u0000aufirst\";s:1:\"T\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:9:\"MORGUL, A\";i:1;s:8:\"AYDIN, N\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:105:\"Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits\";s:8:\"\u0000*\u0000place\";s:9:\"Stevenage\";s:6:\"\u0000*\u0000pub\";s:35:\"Institution of Electrical Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"8\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
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