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Recent advances in modeling the underfill process in flip-chip packaging

Author
WAN, J. W1 ; ZHANG, W. J2 ; BERGSTROM, D. J2
[1] Guangzhou University, China
[2] Department of Mechanical Engineering, University of Saskatchewan, 57 Campus Dr, Saskatoon, Sask., S7N 5A9, Canada
Source

Microelectronics journal. 2007, Vol 38, Num 1, pp 67-75, 9 p ; ref : 38 ref

ISSN
0959-8324
Scientific domain
Electronics
Publisher
Elsevier Science, Oxford
Publication country
United Kingdom
Document type
Article
Language
English
Author keyword
Flip-chip packaging Model Underfill flow
Keyword (fr)
Assemblage brasage tendre Assemblage circuit intégré Composant électronique Contact bosse Contrainte mécanique Dilatation thermique Désadaptation Fiabilité Matrice formage Modélisation Packaging électronique Puce à bosses
Keyword (en)
Soldered joint Integrated circuit bonding Electronic component Solder bump Mechanical stress Thermal expansion Mismatching Reliability Die Modeling Electronic packaging Flip-chip
Keyword (es)
Junta soldada Componente electrónico Contacto con bollos Tensión mecánica Dilatación térmica Desadaptación Fiabilidad Matriz formadora Modelización Packaging electrónico
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
18426899

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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