Conditional data mapping flip-flops for low-power and high-performance systems
- Author
- CHEN KONG TEH1 ; HAMADA, Mototsugu1 ; FUJITA, Tetsuya1 ; HARA, Hiroyuki1 ; IKUMI, Nobuyuki2 ; OOWAKI, Yukihito1
[1] Mobile and Communication System on Chip (SoC) Department, SoC Research and Development Center, Toshiba Corporation, Kawasaki 212-8520, Japan
[2] System on Chip (SoC) Strategic Planning Department, SoC Research and Development Center, Toshiba Corporation, Kawasaki 212-8520, Japan - Source
IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 12, pp 1379-1383, 5 p ; ref : 15 ref
- ISSN
- 1063-8210
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, Piscataway, NJ
- Publication country
- United States
- Document type
- Article
- Language
- English
- Author keyword
- CMOS digital integrated circuits flip-flops high-speed integrated circuits low-power integrated circuits
- Keyword (fr)
- Amplificateur Bistable Circuit déclenchement Circuit intégré numérique CMOS Circuit intégré puissance Circuit intégré rapide Dissipation énergie Electronique faible puissance Etat actuel Etude cas Etude comparative Evaluation performance Fiabilité Haute performance Mappage Temps retard
- Keyword (en)
- Amplifier Bistable Trigger CMOS digital integrated circuits Power integrated circuits High-speed integrated circuits Energy dissipation Low-power electronics State of the art Case study Comparative study Performance evaluation Reliability High performance Mapping Delay time
- Keyword (es)
- Amplificador Biestable Circuito desenganche Disipación energía Estado actual Estudio caso Estudio comparativo Evaluación prestación Fiabilidad Alto rendimiento Carta de datos Tiempo retardo
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A2 Amplifiers
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A6 Digital circuits
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 18458385
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Access to the document
Install on your browser
DOI
10.1109/TVLSI.2006.887833 
https://dx.doi.org/10.1109/TVLSI.2006.887833
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1109\/TVLSI.2006.887833\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:9:\"\u0000*\u0000jtitle\";s:64:\"IEEE transactions on very large scale integration (VLSI) systems\";s:9:\"\u0000*\u0000stitle\";s:51:\"IEEE trans. on very large scale integr. (VLSI) syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:2:\"14\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1379\";s:8:\"\u0000*\u0000epage\";s:4:\"1383\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1063-8210\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"CHEN KONG TEH\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:5:{i:0;s:17:\"HAMADA, Mototsugu\";i:1;s:15:\"FUJITA, Tetsuya\";i:2;s:14:\"HARA, Hiroyuki\";i:3;s:15:\"IKUMI, Nobuyuki\";i:4;s:16:\"OOWAKI, Yukihito\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:8:\"\u0000*\u0000place\";s:14:\"Piscataway, NJ\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"5\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1109\/TVLSI.2006.887833\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:9:\"\u0000*\u0000jtitle\";s:64:\"IEEE transactions on very large scale integration (VLSI) systems\";s:9:\"\u0000*\u0000stitle\";s:51:\"IEEE trans. on very large scale integr. (VLSI) syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:2:\"14\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1379\";s:8:\"\u0000*\u0000epage\";s:4:\"1383\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1063-8210\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"CHEN KONG TEH\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:5:{i:0;s:17:\"HAMADA, Mototsugu\";i:1;s:15:\"FUJITA, Tetsuya\";i:2;s:14:\"HARA, Hiroyuki\";i:3;s:15:\"IKUMI, Nobuyuki\";i:4;s:16:\"OOWAKI, Yukihito\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:8:\"\u0000*\u0000place\";s:14:\"Piscataway, NJ\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"5\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"UnpaywallOpenUrl\":35:{s:8:\"\u0000*\u0000email\";s:27:\"assistance-portail@inist.fr\";s:6:\"\u0000*\u0000fmt\";N;s:6:\"\u0000*\u0000doi\";s:25:\"10.1109\/TVLSI.2006.887833\";s:6:\"\u0000*\u0000pii\";N;s:7:\"\u0000*\u0000pmid\";N;s:9:\"\u0000*\u0000atitle\";N;s:9:\"\u0000*\u0000jtitle\";N;s:9:\"\u0000*\u0000stitle\";N;s:7:\"\u0000*\u0000date\";N;s:9:\"\u0000*\u0000volume\";N;s:8:\"\u0000*\u0000issue\";N;s:8:\"\u0000*\u0000spage\";N;s:8:\"\u0000*\u0000epage\";N;s:8:\"\u0000*\u0000pages\";N;s:7:\"\u0000*\u0000issn\";N;s:8:\"\u0000*\u0000eissn\";N;s:9:\"\u0000*\u0000aulast\";N;s:10:\"\u0000*\u0000aufirst\";N;s:9:\"\u0000*\u0000auinit\";N;s:10:\"\u0000*\u0000auinitm\";N;s:5:\"\u0000*\u0000au\";N;s:9:\"\u0000*\u0000aucorp\";N;s:7:\"\u0000*\u0000isbn\";N;s:8:\"\u0000*\u0000coden\";N;s:8:\"\u0000*\u0000genre\";N;s:7:\"\u0000*\u0000part\";N;s:9:\"\u0000*\u0000btitle\";N;s:8:\"\u0000*\u0000title\";N;s:8:\"\u0000*\u0000place\";N;s:6:\"\u0000*\u0000pub\";N;s:10:\"\u0000*\u0000edition\";N;s:9:\"\u0000*\u0000tpages\";N;s:9:\"\u0000*\u0000series\";N;s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";N;}"
Unpaywall access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1109\/TVLSI.2006.887833\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:9:\"\u0000*\u0000jtitle\";s:64:\"IEEE transactions on very large scale integration (VLSI) systems\";s:9:\"\u0000*\u0000stitle\";s:51:\"IEEE trans. on very large scale integr. (VLSI) syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:2:\"14\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1379\";s:8:\"\u0000*\u0000epage\";s:4:\"1383\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1063-8210\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"CHEN KONG TEH\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:5:{i:0;s:17:\"HAMADA, Mototsugu\";i:1;s:15:\"FUJITA, Tetsuya\";i:2;s:14:\"HARA, Hiroyuki\";i:3;s:15:\"IKUMI, Nobuyuki\";i:4;s:16:\"OOWAKI, Yukihito\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:8:\"\u0000*\u0000place\";s:14:\"Piscataway, NJ\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"5\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:11:\"BaseOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1109\/TVLSI.2006.887833\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:9:\"\u0000*\u0000jtitle\";s:64:\"IEEE transactions on very large scale integration (VLSI) systems\";s:9:\"\u0000*\u0000stitle\";s:51:\"IEEE trans. on very large scale integr. (VLSI) syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:2:\"14\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1379\";s:8:\"\u0000*\u0000epage\";s:4:\"1383\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1063-8210\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"CHEN KONG TEH\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:5:{i:0;s:17:\"HAMADA, Mototsugu\";i:1;s:15:\"FUJITA, Tetsuya\";i:2;s:14:\"HARA, Hiroyuki\";i:3;s:15:\"IKUMI, Nobuyuki\";i:4;s:16:\"OOWAKI, Yukihito\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:8:\"\u0000*\u0000place\";s:14:\"Piscataway, NJ\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"5\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Base Search access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:25:\"10.1109\/TVLSI.2006.887833\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:9:\"\u0000*\u0000jtitle\";s:64:\"IEEE transactions on very large scale integration (VLSI) systems\";s:9:\"\u0000*\u0000stitle\";s:51:\"IEEE trans. on very large scale integr. (VLSI) syst\";s:7:\"\u0000*\u0000date\";s:4:\"2006\";s:9:\"\u0000*\u0000volume\";s:2:\"14\";s:8:\"\u0000*\u0000issue\";s:2:\"12\";s:8:\"\u0000*\u0000spage\";s:4:\"1379\";s:8:\"\u0000*\u0000epage\";s:4:\"1383\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"1063-8210\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"CHEN KONG TEH\";s:10:\"\u0000*\u0000aufirst\";s:0:\"\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:5:{i:0;s:17:\"HAMADA, Mototsugu\";i:1;s:15:\"FUJITA, Tetsuya\";i:2;s:14:\"HARA, Hiroyuki\";i:3;s:15:\"IKUMI, Nobuyuki\";i:4;s:16:\"OOWAKI, Yukihito\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:0:\"\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:78:\"Conditional data mapping flip-flops for low-power and high-performance systems\";s:8:\"\u0000*\u0000place\";s:14:\"Piscataway, NJ\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:1:\"5\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
arXiv access
