In-situ delay characterization and local supply voltage adjustment for compensation of local parametric variations
- Author
- EIREINER, Matthias1 ; HENZLER, Stephan2 ; GEORGAKOS, Georg2 ; BERTHOLD, Joerg2 ; SCHMITT-LANDSIEDEL, Doris1
[1] Institute for Technical Electronics, Technical University of Munich, 80290 Munich, Germany
[2] Infineon Technologies AG, 85579 Neubiberg, Germany - Conference title
- ESSCIRC 2006
- Conference name
- ESSCIRC 2006 European Solid-State Circuits Conference (32 ; Montreux 2006-09-18)
- Author (monograph)
- KAISER, Andreas (Editor)1 ; RUSU, Stefan (Editor)2
Institute of Electrical and Electronics Engineers (IEEE), Solid-State Circuit Society (SSCS), Piscataway, NJ 08854, United States (Organiser of meeting)
[1] Institut d'Electronique, de Microélectronique et de Nanotechnologie, 59046 Lille, France
[2] Intel Corporation, Santa Clara, CA 95052, United States - Source
IEEE journal of solid-state circuits. 2007, Vol 42, Num 7, pp 1583-1592, 10 p ; ref : 18 ref
- CODEN
- IJSCBC
- ISSN
- 0018-9200
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Conference Paper
- Language
- English
- Author keyword
- Adaptive supply voltage (ASV) Razor flip-flop crystal ball flip-flop dynamic voltage scaling (DVS) error detection and correction in-situ characterization local supply voltage assignment
- Keyword (fr)
- Bistable Commutateur semiconducteur puissance Correction erreur Détection erreur In situ Matrice formage Méthode Monte Carlo Régime dynamique Régulation tension Simulation numérique Technologie MOS complémentaire Temps retard
- Keyword (en)
- Bistable Power semiconductor switches Error correction Error detection In situ Die Monte Carlo method Dynamic conditions Voltage regulation Numerical simulation Complementary MOS technology Delay time
- Keyword (es)
- Biestable Corrección error Detección error In situ Matriz formadora Método Monte Carlo Régimen dinámico Regulación voltaje Simulación numérica Tecnología MOS complementario Tiempo retardo
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A6 Digital circuits
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 18943693
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/JSSC.2007.896695 
https://dx.doi.org/10.1109/JSSC.2007.896695
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