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Tri-state map for the minimisation of exclusive-OR switching functions

Author
TRAN, A
Univ. Lowell, dep. electrical eng., Lowell MA 01854, United States
Source

IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 1, pp 16-21, 6 p ; ref : 11 ref

CODEN
IPETD3
ISSN
0143-7062
Scientific domain
Electronics
Publisher
Institution of Electrical Engineers, Stevenage
Publication country
United Kingdom
Document type
Article
Language
English
Keyword (fr)
Circuit logique Minimisation Polynôme Reed Muller
Keyword (en)
Logic circuit Minimization
Keyword (es)
Circuito lógico Minimización
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A6 Digital circuits

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
19487072

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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