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A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain

Author
BAISHYA, Srimanta1 ; MALLIK, Abhijit2 ; CHANDAN KUMAR SARKAR1
[1] Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700 032, India
[2] Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani 741 235, India
Source

Microelectronics and reliability. 2008, Vol 48, Num 1, pp 17-22, 6 p ; ref : 19 ref

CODEN
MCRLAS
ISSN
0026-2714
Scientific domain
Electronics
Publisher
Elsevier, Oxford
Publication country
United Kingdom
Document type
Article
Language
English
Keyword (fr)
Canal court Conception assistée Conception circuit Couche appauvrissement Hauteur barrière Modélisation Méthode analytique Seuil tension Simulateur Transistor MOSFET
Keyword (en)
Short channel Computer aided design Circuit design Depletion layer Barrier height Modeling Analytical method Voltage threshold Simulator MOSFET
Keyword (es)
Canal corto Concepción asistida Diseño circuito Capa empobrecimiento Altura barrera Modelización Método analítico Umbral tensión Simulador
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F04 Transistors

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
20169901

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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