A study of the linearity between Ion and logI offof modern MOS transistors and its application to stress engineering
- Author
- LAU, W. S1 ; PEIZHEN YANG1 ; ENG, C. W2 ; HO, V2 ; LOH, C. H2 ; SIAH, S. Y2 ; VIGAR, D2 ; CHAN, L2
[1] Nunyang Technological University, School of Electrical and Electronic Engineering, Division of Microelectronics, Block S2.1, Nanyang Avenue, Singapore 639798, Singapore
[2] Chartered Semiconductor Manufacturing Ltd., 60 Woodlands Industrial Park D St. 2, Singapore 738406, Singapore - Source
Microelectronics and reliability. 2008, Vol 48, Num 4, pp 497-503, 7 p ; ref : 16 ref
- CODEN
- MCRLAS
- ISSN
- 0026-2714
- Scientific domain
- Electronics
- Publisher
- Elsevier, Oxford
- Publication country
- United Kingdom
- Document type
- Article
- Language
- English
- Keyword (fr)
- Canal n Contrainte traction Hauteur barrière Technologie PMOS Transistor MOS
- Keyword (en)
- n channel Tensile stress Barrier height PMOS technology MOS transistor
- Keyword (es)
- Canal n Tensión traccíon Altura barrera Tecnología PMOS Transistor MOS
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F04 Transistors
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 20349424
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1016/j.microrel.2007.10.002 
https://dx.doi.org/10.1016/j.microrel.2007.10.002
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