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Modelling MOSFET gate length variability for future technology nodes

Author
PATSIS, G. P1 2 3
[1] Institute of Microelectronics, NCSR 'Demokritos', 15310 Athens, Greece
[2] Department of Electronics, TEI of Athens, 12210 Aegaleo, Greece
[3] Department of Electronics, TEI ofPeiraias, 12244 Aegaleo, Greece
Conference name
International Conference on Micro-Nanoelectronics, Nanotechnology and MEMs (Micro) (Micro) (3 ; Athens 2007-11-18)
Source

Physica status solidi. A, Applications and materials science (Print). 2008, Vol 205, Num 11, pp 2541-2543, 3 p ; ref : 9 ref

ISSN
1862-6300
Scientific domain
Crystallography; Electronics; Nanotechnologies, nanostructures, nanoobjects; Condensed state physics
Publisher
Wiley-VCH, Berlin
Publication country
Germany
Document type
Conference Paper
Language
English
Keyword (fr)
Caractéristique électrique Courant drain Désadaptation Langage VHDL Largeur raie Logiciel Loi normale Matrice formage Modélisation Rugosité Transistor MOSFET
Keyword (en)
Electrical characteristic Drain current Mismatching VHDL language Line width Software Gaussian distribution Die Modeling Roughness MOSFET
Keyword (es)
Característica eléctrica Corriente dren Desadaptación Lenguaje VHDL Anchura raya espectral Logicial Curva Gauss Matriz formadora Modelización Rugosidad
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F04 Transistors

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
20860216

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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