A VLSI architecture for arithmetic coding of multilevel images
- Author
- BOO, M1 ; BRUGUERA, J. D1 ; LANG, T1
[1] Department of Electrical and Computer Engineering, University of California at Irvine, Irvine, CA 92664, United States - Source
IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1998, Vol 45, Num 1, pp 163-168 ; ref : 14 ref
- CODEN
- ICSPE5
- ISSN
- 1057-7130
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Circuit VLSI Circuit intégré Code arithmétique Signal multiniveau Système redondant Traitement image
- Keyword (en)
- VLSI circuit Integrated circuit Arithmetic code Multilevel signal Redundant system Image processing
- Keyword (es)
- Circuito VLSI Circuito integrado Código aritmético Señal niveles multiples Sistema redundante Procesamiento imagen
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 2178014
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/82.659470 
https://dx.doi.org/10.1109/82.659470
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