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Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs

Author
TAKEDA, Koichi1 ; SAITO, Toshio2 ; ASAYAMA, Shinobu3 ; AIMOTO, Yoshiharu2 ; KOBATAKE, Hiroyuki2 ; ITO, Shinya4 ; TAKAHASHI, Toshifumi4 ; NOMURA, Masahiro1 ; TAKEUCHI, Kiyoshi5 ; HAYASHI, Yoshihiro5
[1] LSI Research Laboratory, Renesas Electronics, Kawasaki, Kanagawa 211-8668, Japan
[2] Memory IP Development Department, Renesas Electronics, Kawasaki 211-8668, Japan
[3] Memory IP Development Department, Renesas Electronics, Sagamihara, 252-5298, Japan
[4] Renesas Electronics, Embedded Memory Technology Department, Sagamihara 252-5298, Japan
[5] LSI Research Laboratory, Renesas Electronics, Sagamihara 252-5298, Japan
Conference title
Special Issue on the 2010 Symposium on VLSI Circuits
Conference name
2010 Symposium on VLSI Circuits (23 ; Honolulu, Hawaii 2010-06-15)
Author (monograph)
AMERASEKERA, Ajith (Editor)1 ; NAGATA, Makoto (Editor)2
IEEE Solid-State Circuits Society, Piscataway NJ, United States (Organiser of meeting)
Japan Society of Applied Physics, Japan (Organiser of meeting)
[1] Texas Instruments Incorporated, Dallas, TX, United States
[2] Kobe University, Kobe, Japan
Source

IEEE journal of solid-state circuits. 2011, Vol 46, Num 4, pp 806-814, 9 p ; ref : 13 ref

CODEN
IJSCBC
ISSN
0018-9200
Scientific domain
Electronics
Publisher
Institute of Electrical and Electronics Engineers, New York, NY
Publication country
United States
Document type
Conference Paper
Language
English
Author keyword
SRAM scaling Static random access memory (SRAM) static noise margin write margin
Keyword (fr)
Alimentation électrique Circuit intégré Densité élevée Domaine temps ns Electronique puissance Miniaturisation Mémoire accès direct statique Méthode multipas Temps accès Temps retard Mémoire accès direct Mémoire non volatile
Keyword (en)
Power supply Integrated circuit High density ns range Power electronics Miniaturization Static random access memory Multistep method Access time Delay time Random access memory Non volatile memory
Keyword (es)
Alimentación eléctrica Circuito integrado Densidad elevada Electrónica potencia Miniaturización Método multipaso Tiempo acceso Tiempo retardo Memoria acceso directo Memoria no volátil
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03D Electronic equipment and fabrication. Passive components, printed wiring boards, connectics

Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing

Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)

Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D05 Electrical engineering. Electrical power engineering / 001D05H Power electronics, power supplies

Discipline
Electrical engineering. Electroenergetics Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
24154046

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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