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Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator

Author
BERKELAAR, M. R. C. M1 ; BUURMAN, P. H. W2 ; JESS, J. A. G1
[1] Eindhoven University of Technology, 5600 MB Eindhoven, Netherlands
[2] Xirion BV, de Meern, Netherlands
Source

IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 11, pp 1424-1434 ; ref : 24 ref

CODEN
ITCSDI
ISSN
0278-0070
Scientific domain
Electronics
Publisher
Institute of Electrical and Electronics Engineers, New York, NY
Publication country
United States
Document type
Article
Language
English
Keyword (fr)
Circuit intégré Circuit logique Conception assistée Conception circuit Modélisation Optimisation Simulation
Keyword (en)
Integrated circuit Logic circuit Computer aided design Circuit design Modeling Optimization Simulation
Keyword (es)
Circuito integrado Circuito lógico Concepción asistida Concepción circuito Modelización Optimización Simulación
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
2496167

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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