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Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters

Author
MOHANTY, B. K1 ; MEHER, P. K2
[1] S.K.C.G. College, Department of Physics, Paralakhemundi, Orissa 761 200, India
[2] Berhampur University, Department of Electronic Sciences, Berhampur, Orissa 760007, India
Source

IEE proceedings. Computers and digital techniques. 1996, Vol 143, Num 6, pp 436-439 ; ref : 8 ref

ISSN
1350-2387
Scientific domain
Electronics; Computer science; Telecommunications
Publisher
Institution of Electrical Engineers, Stevenage
Publication country
United Kingdom
Document type
Article
Language
English
Keyword (fr)
Circuit VLSI Conception circuit Filtre bidimensionnel Filtre réponse impulsion finie Implémentation Phase linéaire Réseau systolique Système parallèle
Keyword (en)
VLSI circuit Circuit design Two dimensional filter Finite impulse response filter Implementation Linear phase Systolic network Parallel system
Keyword (es)
Circuito VLSI Concepción circuito Filtro bidimensional Filtro respuesta impulsión acabada Ejecución Fase lineal Red sistólica Sistema paralelo
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
2573928

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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