Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture
- Author
- UENG, Yeong-Luh1 ; WANG, Yu-Luen2 ; KAN, Li-Sheng3 ; YANG, Chung-Jay4 ; SU, Yung-Hsiang4
[1] Department of Electrical Engineering and the Institute of Communications Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan, Province of China
[2] MediaTek Inc., Science Park, Hsinchu 30075, Taiwan, Province of China
[3] Silicon Motion Technology Corporation, Hsinchu County 30265, Taiwan, Province of China
[4] Department of Electrical Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan, Province of China - Source
IEEE transactions on signal processing. 2012, Vol 60, Num 8, pp 4387-4402, 16 p ; ref : 35 ref
- CODEN
- ITPRED
- ISSN
- 1053-587X
- Scientific domain
- Telecommunications
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Author keyword
- VLSI low-density s parity-check (LDPC) convolutional codes s—Convolutional codes (CCs)
- Keyword (fr)
- Circuit VLSI Code contrôle parité Code convolutif Contrôle parité Coût production Débit information Décodage Envoi message Estimation erreur Faisabilité Gestion mémoire Horloge Implémentation Minimisation coût Méthode itérative Parallélisation Technologie MOS complémentaire Traitement signal Transmission haut débit Transmission information Variation temporelle Code correcteur erreur
- Keyword (en)
- VLSI circuit Parity check codes Convolutional code Parity check Production cost Information rate Decoding Message passing Error estimation Feasibility Storage management Clock Implementation Cost minimization Iterative method Parallelization Complementary MOS technology Signal processing High rate transmission Information transmission Time variation Error correcting code
- Keyword (es)
- Circuito VLSI Código convolutivo Control paridad Coste producción Índice información Desciframiento Estimación error Practicabilidad Gestión memoria Reloj Implementación Minimización costo Método iterativo Paralelisacíon Tecnología MOS complementario Procesamiento señal Transmisión alta caudal Transmisión información Variación temporal Código corrector error
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D04 Telecommunications and information theory / 001D04A Information, signal and communications theory / 001D04A04 Signal and communications theory / 001D04A04A Signal, noise / 001D04A04A2 Detection, estimation, filtering, equalization, prediction
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D04 Telecommunications and information theory / 001D04A Information, signal and communications theory / 001D04A04 Signal and communications theory / 001D04A04B Coding, codes
- Discipline
- Telecommunications and information theory
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 26185785
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/TSP.2012.2197749 
https://dx.doi.org/10.1109/TSP.2012.2197749
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