Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
- Author
- FENG LIANG1 ; LUWEN ZHANG1 ; SHAOCHONG LEI1 ; GUOHE ZHANG1 ; KAILE GAO1 ; BIN LIANG1
[1] School of Electronic and Information Engineering, Xi'an Jiaotong University, Xi'an 710049, China - Source
IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 4, pp 614-623, 10 p ; ref : 25 ref
- ISSN
- 1063-8210
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Author keyword
- -Built-in self-test (BIST) low power single-input change (SIC) test pattern generator (TPG)
- Keyword (fr)
- Architecture reconfigurable Autotest Carbure de silicium Electronique faible puissance Evaluation performance Extensibilité Génération vecteur test Horloge Loi uniforme SiC
- Keyword (en)
- Reconfigurable architectures Built in self test Silicon carbide Low-power electronics Performance evaluation Scalability Test pattern generation Clock Uniform distribution
- Keyword (es)
- Autoprueba Silicio carburo Evaluación prestación Estensibilidad Generación vector prueba Reloj Ley uniforme
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03B Testing, measurement, noise and reliability
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 27194647
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/TVLSI.2012.2195689 
https://dx.doi.org/10.1109/TVLSI.2012.2195689
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