A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy
- Author
- JEON, Hyung-Joon1 ; KULKARNI, Raghavendra2 ; LO, Yung-Chung3 ; JUSUNG KIM3 ; SILVA-MARTINEZ, Jose1
[1] Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 77843, United States
[2] Broadcom Corporation, Sunnyvale, CA 94086, United States
[3] Qualcomm Inc., San Diego, CA 92121, United States - Source
IEEE journal of solid-state circuits. 2013, Vol 48, Num 6, pp 1398-1415, 18 p ; ref : 31 ref
- CODEN
- IJSCBC
- ISSN
- 0018-9200
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Author keyword
- Clock and data recovery (CDR) adaptive loop gain bang-bang phase detector (BBPD) bit-error-rate (BER) charge pump (CP) current-mode logic (CML) jitter tolerance (JTOL) jitter
- Keyword (fr)
- Analyse spectre Circuit de verrouillage Détecteur phase Effet non linéaire Estimation a priori Estimation signal Evaluation performance Gain puissance Gigue Implémentation Logique mode courant Montage cascode Méthode adaptative Phénomène non linéaire Pompage charge Prototype Reconstitution rythme Récupération de données Taux erreur bit Technologie MOS complémentaire Valeur efficace Circuit à faible gigue
- Keyword (en)
- Spectrum analysis Latch circuit Phase detector Non linear effect A priori estimation Signal estimation Performance evaluation Power gain Jitter Implementation Current-mode logic Cascode connection Adaptive method Non linear phenomenon Charge pumping Prototype Clock recovery Data recovery Bit error rate Complementary MOS technology Root mean square value Low-jitter circuit
- Keyword (es)
- Análisis espectro Circuito de enganche Detector fase Efecto no lineal Estimación a priori Estimación señal Evaluación prestación Aumento potencia Fluctuación Implementación Montaje cascode Método adaptativo Fenómeno no lineal Bombeo carga Prototipo Recuperación de reloj Recuperación de datos Tasa error bit Tecnología MOS complementario Valor eficaz
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 27485082
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/JSSC.2013.2253414 
https://dx.doi.org/10.1109/JSSC.2013.2253414
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