A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique
- Author
- HYUNG SEOK KIM1 ; ORNELAS, Carlos1 ; CHANDRASHEKAR, Kailash1 ; DAN SHI1 ; SU, Pin-En2 ; MADOGLIO, Paolo1 ; LI, William Y1 ; RAVI, Ashoke1
[1] Intel Corporation, Hillsboro, OR 97124, United States
[2] Broadcom Corporation, Irvine, CA 92617, United States - Conference title
- SPECIAL ISSUE ON THE 38TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC)
- Conference name
- ESSCIRC 2012 European Solid-State Circuits Conference (38 ; Bordeaux 2012-09-17)
- Author (monograph)
- LISCIDINI, Antonio (Editor)1 ; SMITH, Douglas (Editor)
[1] The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON M5S 3G4, Canada - Source
IEEE journal of solid-state circuits. 2013, Vol 48, Num 7, pp 1721-1729, 9 p ; ref : 22 ref
- CODEN
- IJSCBC
- ISSN
- 0018-9200
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Conference Paper
- Language
- English
- Author keyword
- DPLL WiFi WiMax fractional-n mismatch insensitive TDC
- Keyword (fr)
- Boucle verrouillage fréquence Boucle verrouillage phase Bruit phase Circuit bistable Circuit intégré Convertisseur NA Convertisseur signal Désadaptation Echantillonnage Etalonnage Linéarisation Méthode cas pire Oscillateur commande tension Radiocommunication Réponse dynamique Réseau local sans fil Système sur puce Technologie MOS complémentaire Temps retard Transmission longue distance Télécommunication sans fil Conversion temps numérique Circuit séquentiel
- Keyword (en)
- Frequency locked loops Phase locked loop Phase noise Flip-flop circuits Integrated circuit DA converter Signal converter Mismatching Sampling Calibration Linearization Worst case method Voltage controlled oscillator Radio communication Dynamic response Wireless LAN System on a chip Complementary MOS technology Delay time Long distance transmission Wireless telecommunication Time to digital conversion Sequential circuit
- Keyword (es)
- Bucle enclavamiento fase Ruido fase Circuito integrado Convertidor NA Convertidor señal Desadaptación Muestreo Contraste Linearización Método caso peor Oscilador comando tensión Radiocomunicación Respuesta dinámica Sistema sobre pastilla Tecnología MOS complementario Tiempo retardo Transmisión larga distancia Telecomunicación sin hilo Circuito secuencial
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A4 Signal convertors
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A5 Circuits of signal characteristics conditioning (including delay circuits)
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A6 Digital circuits
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 27678031
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/JSSC.2013.2253407 
https://dx.doi.org/10.1109/JSSC.2013.2253407
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