A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC
- Autor
- TONER, M. F; ROBERTS, G. W
McGill univ., dep. electrical eng. microelectronics, Montreal PQ H3A 2A7, Canada - Fuente
IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1995, Vol 42, Num 1, pp 1-15 ; ref : 18 ref
- CODEN
- ICSPE5
- ISSN
- 1057-7130
- Campo Científico
- Electronics
- Editor
- Institute of Electrical and Electronics Engineers, New York, NY
- País de la publicación
- United States
- Tipo de documento
- Article
- Idioma
- English
- Palabra clave (fr)
- Circuit VLSI Circuit intégré Convertisseur AN Essai Gainage Méthode essai Rapport signal bruit Réponse fréquence
- Palabra clave (in)
- VLSI circuit Integrated circuit AD converter Test Sheathing Test method Signal to noise ratio Frequency response
- Palabra clave (es)
- Circuito VLSI Circuito integrado Convertidor AN Ensayo Envolvente Método ensayo Relación señal ruido Respuesta frecuencia
- Clasificación
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Disciplina
- Electronics
- Procedencia
- Inist-CNRS
- Base de datos
- PASCAL
- Identificador INIST
- 3428342
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/82.363546 
https://dx.doi.org/10.1109/82.363546
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