Partitioning of processor arrays: a piecewise regular approach
- Author
- TEICH, J; THIELE, L
Univ. Saarland, inst. microelectronics, 6600 Saarbrücken, Germany - Source
Integration (Amsterdam). 1993, Vol 14, Num 3, pp 297-332 ; ref : 36 ref
- CODEN
- IVJODL
- ISSN
- 0167-9260
- Scientific domain
- Electronics
- Publisher
- Elsevier Science, Amsterdam
- Publication country
- Netherlands
- Document type
- Article
- Language
- English
- Keyword (fr)
- Algorithme parallèle Architecture ordinateur Circuit VLSI Conception système Etude théorique Graphe régulier Partition Processeur tableau Transformation programme Clustering Mapping Tableau dimension fixe Transformation algorithme
- Keyword (en)
- Parallel algorithm Computer architecture VLSI circuit System design Theoretical study Regular graph Partition Array processor Program transformation
- Keyword (es)
- Algoritmo paralelo Arquitectura ordenador Circuito VLSI Concepción sistema Estudio teórico Grafo regular Partición Procesador panel Transformación programa
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 3909502
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1016/0167-9260(93)90013-3 
https://dx.doi.org/10.1016/0167-9260(93)90013-3
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