Subthreshold-current reduction circuits for multi-gigabit DRAM's
- Author
- SAKATA, T; ITOH, K; HORIGUCHI, M; AOKI, M
Hitachi Ltd, cent. res. lab., Kokubunji, Tokyo 185, Japan - Source
IEEE journal of solid-state circuits. 1994, Vol 29, Num 7, pp 761-769 ; ref : 17 ref
- CODEN
- IJSCBC
- ISSN
- 0018-9200
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Alimentation électrique Caractéristique électrique Circuit intégré Etude théorique Limiteur courant Mémoire accès direct Mémoire dynamique Méthode itérative
- Keyword (en)
- Power supply Electrical characteristic Integrated circuit Theoretical study Current limiter Random access memory(RAM) Dynamical storage Iterative method
- Keyword (es)
- Alimentación eléctrica Característica eléctrica Circuito integrado Estudio teórico Limitador corriente Memoria acceso directo Memoria dinámica Método iterativo
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 4179554
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/4.303713 
https://dx.doi.org/10.1109/4.303713
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