Stuck fault test generation for dynamic CMOS
- Author
- ISMAEEL, A. A
Univ. Kuwait, dep. electrical computer eng., Safat 13060, Kuwait - Source
Microelectronics and reliability. 1994, Vol 34, Num 10, pp 1597-1613 ; ref : 12 ref
- CODEN
- MCRLAS
- ISSN
- 0026-2714
- Scientific domain
- Electronics
- Publisher
- Elsevier, Oxford
- Publication country
- United Kingdom
- Document type
- Article
- Language
- English
- Keyword (fr)
- Circuit MOS Circuit combinatoire Circuit dynamique Circuit intégré Circuit logique Détection panne Essai Fiabilité Fonction logique Modélisation Méthode essai Technologie MOS complémentaire
- Keyword (en)
- MOS circuit Combinatory circuit Dynamic circuit Integrated circuit Logic circuit Failure detection Test Reliability Logical function Modeling Test method Complementary MOS technology
- Keyword (es)
- Circuito MOS Circuito combinatorio Circuito dinámico Circuito integrado Circuito lógico Detección falla Ensayo Fiabilidad Función lógica Modelización Método ensayo Tecnología MOS complementario
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03B Testing, measurement, noise and reliability
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 4258438
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1016/0026-2714(94)90045-0 
https://dx.doi.org/10.1016/0026-2714(94)90045-0
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