A reconfigurable VLSI neural network
- Author
- SATYANARAYANA, S; TSIVIDIS, Y. P; GRAF, H. P
Philips Laboratories, Briarcliff Manor NY 10510, United States - Source
IEEE journal of solid-state circuits. 1992, Vol 27, Num 1, pp 67-81 ; ref : 28 ref
- CODEN
- IJSCBC
- ISSN
- 0018-9200
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Algorithme Apprentissage Bloc diagramme Circuit VLSI Circuit intégré Conception circuit Configuration géométrique Etude expérimentale Implémentation Matériel(informatique) Modélisation Performance Puce électronique Reconfiguration Réseau neuronal Technologie MOS complémentaire Topologie
- Keyword (en)
- Algorithm Learning Block diagram VLSI circuit Integrated circuit Circuit design Geometrical configuration Experimental study Implementation Hardware Modeling Performance Chip Reconfiguration Neural network Complementary MOS technology Topology
- Keyword (es)
- Algoritmo Aprendizaje Diagrama conjunto Circuito VLSI Circuito integrado Concepción circuito Configuración geométrica Estudio experimental Ejecución Material (informática) Modelización Rendimiento Pastilla electrónica Reconfiguración Red neuronal Tecnología MOS complementario Topología
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 5111219
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Access to the document
Install on your browser
DOI
10.1109/4.109558 
https://dx.doi.org/10.1109/4.109558
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:16:\"10.1109\/4.109558\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:36:\"A reconfigurable VLSI neural network\";s:9:\"\u0000*\u0000jtitle\";s:36:\"IEEE journal of solid-state circuits\";s:9:\"\u0000*\u0000stitle\";s:28:\"IEEE j. solid-state circuits\";s:7:\"\u0000*\u0000date\";s:4:\"1992\";s:9:\"\u0000*\u0000volume\";s:2:\"27\";s:8:\"\u0000*\u0000issue\";s:1:\"1\";s:8:\"\u0000*\u0000spage\";s:2:\"67\";s:8:\"\u0000*\u0000epage\";s:2:\"81\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9200\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"SATYANARAYANA\";s:10:\"\u0000*\u0000aufirst\";s:1:\"S\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:14:\"TSIVIDIS, Y. P\";i:1;s:10:\"GRAF, H. P\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"IJSCBC\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:36:\"A reconfigurable VLSI neural network\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:16:\"10.1109\/4.109558\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:36:\"A reconfigurable VLSI neural network\";s:9:\"\u0000*\u0000jtitle\";s:36:\"IEEE journal of solid-state circuits\";s:9:\"\u0000*\u0000stitle\";s:28:\"IEEE j. solid-state circuits\";s:7:\"\u0000*\u0000date\";s:4:\"1992\";s:9:\"\u0000*\u0000volume\";s:2:\"27\";s:8:\"\u0000*\u0000issue\";s:1:\"1\";s:8:\"\u0000*\u0000spage\";s:2:\"67\";s:8:\"\u0000*\u0000epage\";s:2:\"81\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9200\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"SATYANARAYANA\";s:10:\"\u0000*\u0000aufirst\";s:1:\"S\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:14:\"TSIVIDIS, Y. P\";i:1;s:10:\"GRAF, H. P\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"IJSCBC\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:36:\"A reconfigurable VLSI neural network\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"UnpaywallOpenUrl\":35:{s:8:\"\u0000*\u0000email\";s:27:\"assistance-portail@inist.fr\";s:6:\"\u0000*\u0000fmt\";N;s:6:\"\u0000*\u0000doi\";s:16:\"10.1109\/4.109558\";s:6:\"\u0000*\u0000pii\";N;s:7:\"\u0000*\u0000pmid\";N;s:9:\"\u0000*\u0000atitle\";N;s:9:\"\u0000*\u0000jtitle\";N;s:9:\"\u0000*\u0000stitle\";N;s:7:\"\u0000*\u0000date\";N;s:9:\"\u0000*\u0000volume\";N;s:8:\"\u0000*\u0000issue\";N;s:8:\"\u0000*\u0000spage\";N;s:8:\"\u0000*\u0000epage\";N;s:8:\"\u0000*\u0000pages\";N;s:7:\"\u0000*\u0000issn\";N;s:8:\"\u0000*\u0000eissn\";N;s:9:\"\u0000*\u0000aulast\";N;s:10:\"\u0000*\u0000aufirst\";N;s:9:\"\u0000*\u0000auinit\";N;s:10:\"\u0000*\u0000auinitm\";N;s:5:\"\u0000*\u0000au\";N;s:9:\"\u0000*\u0000aucorp\";N;s:7:\"\u0000*\u0000isbn\";N;s:8:\"\u0000*\u0000coden\";N;s:8:\"\u0000*\u0000genre\";N;s:7:\"\u0000*\u0000part\";N;s:9:\"\u0000*\u0000btitle\";N;s:8:\"\u0000*\u0000title\";N;s:8:\"\u0000*\u0000place\";N;s:6:\"\u0000*\u0000pub\";N;s:10:\"\u0000*\u0000edition\";N;s:9:\"\u0000*\u0000tpages\";N;s:9:\"\u0000*\u0000series\";N;s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";N;}"
Unpaywall access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:16:\"10.1109\/4.109558\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:36:\"A reconfigurable VLSI neural network\";s:9:\"\u0000*\u0000jtitle\";s:36:\"IEEE journal of solid-state circuits\";s:9:\"\u0000*\u0000stitle\";s:28:\"IEEE j. solid-state circuits\";s:7:\"\u0000*\u0000date\";s:4:\"1992\";s:9:\"\u0000*\u0000volume\";s:2:\"27\";s:8:\"\u0000*\u0000issue\";s:1:\"1\";s:8:\"\u0000*\u0000spage\";s:2:\"67\";s:8:\"\u0000*\u0000epage\";s:2:\"81\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9200\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"SATYANARAYANA\";s:10:\"\u0000*\u0000aufirst\";s:1:\"S\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:14:\"TSIVIDIS, Y. P\";i:1;s:10:\"GRAF, H. P\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"IJSCBC\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:36:\"A reconfigurable VLSI neural network\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:11:\"BaseOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:16:\"10.1109\/4.109558\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:36:\"A reconfigurable VLSI neural network\";s:9:\"\u0000*\u0000jtitle\";s:36:\"IEEE journal of solid-state circuits\";s:9:\"\u0000*\u0000stitle\";s:28:\"IEEE j. solid-state circuits\";s:7:\"\u0000*\u0000date\";s:4:\"1992\";s:9:\"\u0000*\u0000volume\";s:2:\"27\";s:8:\"\u0000*\u0000issue\";s:1:\"1\";s:8:\"\u0000*\u0000spage\";s:2:\"67\";s:8:\"\u0000*\u0000epage\";s:2:\"81\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9200\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"SATYANARAYANA\";s:10:\"\u0000*\u0000aufirst\";s:1:\"S\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:14:\"TSIVIDIS, Y. P\";i:1;s:10:\"GRAF, H. P\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"IJSCBC\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:36:\"A reconfigurable VLSI neural network\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Base Search access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:16:\"10.1109\/4.109558\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:36:\"A reconfigurable VLSI neural network\";s:9:\"\u0000*\u0000jtitle\";s:36:\"IEEE journal of solid-state circuits\";s:9:\"\u0000*\u0000stitle\";s:28:\"IEEE j. solid-state circuits\";s:7:\"\u0000*\u0000date\";s:4:\"1992\";s:9:\"\u0000*\u0000volume\";s:2:\"27\";s:8:\"\u0000*\u0000issue\";s:1:\"1\";s:8:\"\u0000*\u0000spage\";s:2:\"67\";s:8:\"\u0000*\u0000epage\";s:2:\"81\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9200\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:13:\"SATYANARAYANA\";s:10:\"\u0000*\u0000aufirst\";s:1:\"S\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:2:{i:0;s:14:\"TSIVIDIS, Y. P\";i:1;s:10:\"GRAF, H. P\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"IJSCBC\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:36:\"A reconfigurable VLSI neural network\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
arXiv access
