Validation of a VLSI chip using hierarchical colored Petri Nets
- Author
- SHAPIRO, R. M
Meta Software Corp., Cambridge MA 02140, United States - Source
Microelectronics and reliability. 1991, Vol 31, Num 4, pp 607-625 ; ref : 14 ref
- CODEN
- MCRLAS
- ISSN
- 0026-2714
- Scientific domain
- Electronics
- Publisher
- Elsevier, Oxford
- Publication country
- United Kingdom
- Document type
- Article
- Language
- English
- Keyword (fr)
- Circuit VLSI Filtre numérique Matériel(informatique) Modélisation Performance Registre Réseau Pétri Système hiérarchisé
- Keyword (en)
- VLSI circuit Digital filter Hardware Modeling Performance Register Petri net Hierarchical system
- Keyword (es)
- Circuito VLSI Filtro numérico Material (informática) Modelización Rendimiento Registro Red Petri Sistema jerarquizado
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 5248437
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1016/0026-2714(91)90006-S 
https://dx.doi.org/10.1016/0026-2714(91)90006-S
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