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A 1-V operating 256-kb full-CMOS SRAM

Author
SEKIYAMA, A; SEKI, T; NAGAI, S; IWASE, A; SUZUKI, N; HAYASAKA, M
Fujitsu VLSI Ltd, MOS LSI design div., Kasugai 487, Japan
Source

IEEE journal of solid-state circuits. 1992, Vol 27, Num 5, pp 776-782 ; ref : 5 ref

CODEN
IJSCBC
ISSN
0018-9200
Scientific domain
Electronics
Publisher
Institute of Electrical and Electronics Engineers, New York, NY
Publication country
United States
Document type
Article
Language
English
Keyword (fr)
Caractéristique courant tension Circuit intégré Circuit retard Conception circuit Etude théorique Mémoire accès direct Mémoire statique Performance Technologie MOS complémentaire Tension électrique
Keyword (en)
Voltage current curve Integrated circuit Delay circuit Circuit design Theoretical study Random access memory(RAM) Static storage Performance Complementary MOS technology Voltage
Keyword (es)
Característica corriente tensión Circuito integrado Circuito retardo Concepción circuito Estudio teórico Memoria acceso directo Memoria estática Rendimiento Tecnología MOS complementario Voltaje
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
5277157

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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