A recursive technique for computing delays in series-parallel MOS transistor circuits
- Author
- CAISSO, J.-P; CERNY, E; RUMIN, N. C
McGill univ., dep. electrical eng., VLSI design lab., Montreal PQ H3A 2A7, Canada - Source
IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 5, pp 589-595 ; ref : 13 ref
- CODEN
- ITCSDI
- ISSN
- 0278-0070
- Scientific domain
- Electronics
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Algorithme Circuit RC Circuit VLSI Circuit intégré Montage série parallèle Méthode récursive Technologie MOS Temps retard TREE
- Keyword (en)
- Algorithm RC circuit VLSI circuit Integrated circuit Series parallel connection Recursive method MOS technology Delay time
- Keyword (es)
- Algoritmo Circuito RC Circuito VLSI Circuito integrado Montaje serie paralelo Método recursivo Tecnología MOS Tiempo retardo
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 5343847
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/43.79496 
https://dx.doi.org/10.1109/43.79496
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