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A sub-10 ps/gate direct-coupled FET logic circuit with 0.2μm-gate GaAs MESFET

Author
TSUJI, H; INOMATA FUJISHIRO, H; NAKAMURA, H; NISHI, S
Oki Electric Industry Co., Ltd, res. development group, semiconductor technology lab., Hachioji-shi, Tokyo 193, Japan
Source

Japanese journal of applied physics. 1990, Vol 29, Num 12, pp L2438-L2441 ; 2 ; ref : 7 ref

CODEN
JJAPA5
ISSN
0021-4922
Scientific domain
Crystallography; Optics; Condensed state physics; Physics; Plasma physics
Publisher
Japanese journal of applied physics, Tokyo
Publication country
Japan
Document type
Article
Language
English
Keyword (fr)
Circuit logique Couche multiple Couplage Fabrication microélectronique Gallium Arséniure Grille transistor Photorésist Transistor effet champ barrière Schottky
Keyword (en)
Logic circuit Multiple layer Coupling Microelectronic fabrication Gallium Arsenides Transistor gate Photoresist Metal semiconductor field effect transistor
Keyword (es)
Circuito lógico Capa múltiple Acoplamiento Fabricación microeléctrica Galio Arseniuro Rejilla transistor Fotorresistente Transistor efecto campo barrera Schottky
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
5378659

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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