A parallel pipelined dataflow trigger processor
- Author
- LEE, C; MILLER, G; KAPLAN, D. M; SA, J; HSIUNG, Y. B; CAREY, T; JEPPESEN, R
Northern Illinois univ., DeKalb IL 60115, United States - Source
IEEE transactions on nuclear science. 1991, Vol 38, Num 2, pp 461-470 ; 1 ; ref : 6 ref
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Algorithme Circuit déclenchement Circuit intégré Etude expérimentale Etude théorique Implémentation Processeur
- Keyword (en)
- Algorithm Trigger Integrated circuit Experimental study Theoretical study Implementation Processor
- Keyword (es)
- Algoritmo Circuito desenganche Circuito integrado Estudio experimental Estudio teórico Ejecución Procesador
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06B Integrated circuits by function (including memories and processors)
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 5437857
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/23.289340 
https://dx.doi.org/10.1109/23.289340
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