Full systolic binary multiplier
- Author
- ARECHABALA, J; BOEMO, E. I; MENESES, J; MORENO, F; LOPEZ BARRIO, C
Univ. politécn. Madrid, ETSI telecommunicación, 28040 Madrid, Spain - Issue title
- Teaching and research initiatives in VLSI design
- Source
IEE proceedings. Part G. Circuits devices and systems. 1992, Vol 139, Num 2, pp 188-190 ; ref : 5 ref
- CODEN
- IPPSDL
- ISSN
- 0956-3768
- Scientific domain
- Electronics
- Publisher
- Institution of Electrical Engineers, London
- Publication country
- United Kingdom
- Document type
- Article
- Language
- English
- Keyword (fr)
- Conception circuit Etude théorique Multiplicateur Performance Processeur Réseau systolique
- Keyword (en)
- Circuit design Theoretical study Multiplier Performance Processor Systolic network
- Keyword (es)
- Concepción circuito Estudio teórico Multiplicador Rendimiento Procesador Red sistólica
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits / 001D03F06A Design. Technologies. Operation analysis. Testing
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 5584408
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1049/ip-g-2.1992.0032 
https://dx.doi.org/10.1049/ip-g-2.1992.0032
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