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A VLSI neural processor for image data compression using self-organization networks

Author
WAI-CHI FANG; SHEU, B. J; CHEN, O. T.-C; CHOI, J
Univ. Southern California, signal image processing inst., dep. electrical eng., Los Angeles CA 90089-0271, United States
Source

IEEE transactions on neural networks. 1992, Vol 3, Num 3, pp 506-517 ; ref : 31 ref

CODEN
ITNNEP
ISSN
1045-9227
Scientific domain
Electronics; Computer science; Psychology, psychopathology, psychiatry
Publisher
Institute of Electrical and Electronics Engineers, New York, NY
Publication country
United States
Document type
Article
Language
English
Keyword (fr)
Algorithme Apprentissage Circuit VLSI Circuit intégré Compression donnée Conception circuit Implantation(topométrie) Processeur Réalisation circuit Réseau neuronal Traitement image
Keyword (en)
Algorithm Learning VLSI circuit Integrated circuit Data compression Circuit design Layout Processor Circuit realization Neural network Image processing
Keyword (es)
Algoritmo Aprendizaje Circuito VLSI Circuito integrado Compresión dato Concepción circuito Implantación(topometría) Procesador Realización circuito Red neuronal Procesamiento imagen
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G03 Neural networks

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
5612689

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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