Testable realizations for FET stuck-open faults in CMOS combinational logic circuits
- Author
- REDDY, S. M1 ; REDDY, M. K
[1] Univ., dep. electrical computer eng., Iowa City IA 52242, United States - Source
IEEE transactions on computers. 1986, Vol 35, Num 8, pp 742-754 ; ref : 20 ref
- CODEN
- ITCOB4
- ISSN
- 0018-9340
- Scientific domain
- Computer science
- Publisher
- Institute of Electrical and Electronics Engineers, New York, NY
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Circuit combinatoire Circuit logique Essai Panne Technologie MOS complémentaire
- Keyword (en)
- Combinatory circuit Logic circuit Test Breakdown Complementary MOS technology
- Keyword (es)
- Circuito combinatorio Circuito logico Ensayo Pana Tecnología MOS complementario
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03G Electric, optical and optoelectronic circuits / 001D03G02 Circuit properties / 001D03G02A Electronic circuits / 001D03G02A6 Digital circuits
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 8066967
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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DOI
10.1109/TC.1986.1676825 
https://dx.doi.org/10.1109/TC.1986.1676825
"O:13:\"PanistOpenUrl\":36:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000idc\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TC.1986.1676825\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:30:\"IEEE transactions on computers\";s:9:\"\u0000*\u0000stitle\";s:18:\"IEEE trans. comput\";s:7:\"\u0000*\u0000date\";s:4:\"1986\";s:9:\"\u0000*\u0000volume\";s:2:\"35\";s:8:\"\u0000*\u0000issue\";s:1:\"8\";s:8:\"\u0000*\u0000spage\";s:3:\"742\";s:8:\"\u0000*\u0000epage\";s:3:\"754\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9340\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"REDDY\";s:10:\"\u0000*\u0000aufirst\";s:4:\"S. M\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:11:\"REDDY, M. K\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"ITCOB4\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Panist access
"O:12:\"IstexOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TC.1986.1676825\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:30:\"IEEE transactions on computers\";s:9:\"\u0000*\u0000stitle\";s:18:\"IEEE trans. comput\";s:7:\"\u0000*\u0000date\";s:4:\"1986\";s:9:\"\u0000*\u0000volume\";s:2:\"35\";s:8:\"\u0000*\u0000issue\";s:1:\"8\";s:8:\"\u0000*\u0000spage\";s:3:\"742\";s:8:\"\u0000*\u0000epage\";s:3:\"754\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9340\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"REDDY\";s:10:\"\u0000*\u0000aufirst\";s:4:\"S. M\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:11:\"REDDY, M. K\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"ITCOB4\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Istex access
"O:16:\"UnpaywallOpenUrl\":35:{s:8:\"\u0000*\u0000email\";s:27:\"assistance-portail@inist.fr\";s:6:\"\u0000*\u0000fmt\";N;s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TC.1986.1676825\";s:6:\"\u0000*\u0000pii\";N;s:7:\"\u0000*\u0000pmid\";N;s:9:\"\u0000*\u0000atitle\";N;s:9:\"\u0000*\u0000jtitle\";N;s:9:\"\u0000*\u0000stitle\";N;s:7:\"\u0000*\u0000date\";N;s:9:\"\u0000*\u0000volume\";N;s:8:\"\u0000*\u0000issue\";N;s:8:\"\u0000*\u0000spage\";N;s:8:\"\u0000*\u0000epage\";N;s:8:\"\u0000*\u0000pages\";N;s:7:\"\u0000*\u0000issn\";N;s:8:\"\u0000*\u0000eissn\";N;s:9:\"\u0000*\u0000aulast\";N;s:10:\"\u0000*\u0000aufirst\";N;s:9:\"\u0000*\u0000auinit\";N;s:10:\"\u0000*\u0000auinitm\";N;s:5:\"\u0000*\u0000au\";N;s:9:\"\u0000*\u0000aucorp\";N;s:7:\"\u0000*\u0000isbn\";N;s:8:\"\u0000*\u0000coden\";N;s:8:\"\u0000*\u0000genre\";N;s:7:\"\u0000*\u0000part\";N;s:9:\"\u0000*\u0000btitle\";N;s:8:\"\u0000*\u0000title\";N;s:8:\"\u0000*\u0000place\";N;s:6:\"\u0000*\u0000pub\";N;s:10:\"\u0000*\u0000edition\";N;s:9:\"\u0000*\u0000tpages\";N;s:9:\"\u0000*\u0000series\";N;s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";N;}"
Unpaywall access
"O:16:\"EuropePMCOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TC.1986.1676825\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:30:\"IEEE transactions on computers\";s:9:\"\u0000*\u0000stitle\";s:18:\"IEEE trans. comput\";s:7:\"\u0000*\u0000date\";s:4:\"1986\";s:9:\"\u0000*\u0000volume\";s:2:\"35\";s:8:\"\u0000*\u0000issue\";s:1:\"8\";s:8:\"\u0000*\u0000spage\";s:3:\"742\";s:8:\"\u0000*\u0000epage\";s:3:\"754\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9340\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"REDDY\";s:10:\"\u0000*\u0000aufirst\";s:4:\"S. M\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:11:\"REDDY, M. K\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"ITCOB4\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Europe PubMed Central access
"O:11:\"BaseOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TC.1986.1676825\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:30:\"IEEE transactions on computers\";s:9:\"\u0000*\u0000stitle\";s:18:\"IEEE trans. comput\";s:7:\"\u0000*\u0000date\";s:4:\"1986\";s:9:\"\u0000*\u0000volume\";s:2:\"35\";s:8:\"\u0000*\u0000issue\";s:1:\"8\";s:8:\"\u0000*\u0000spage\";s:3:\"742\";s:8:\"\u0000*\u0000epage\";s:3:\"754\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9340\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"REDDY\";s:10:\"\u0000*\u0000aufirst\";s:4:\"S. M\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:11:\"REDDY, M. K\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"ITCOB4\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
Base Search access
"O:12:\"ArXivOpenUrl\":35:{s:10:\"\u0000*\u0000openUrl\";N;s:6:\"\u0000*\u0000fmt\";s:7:\"journal\";s:6:\"\u0000*\u0000doi\";s:23:\"10.1109\/TC.1986.1676825\";s:6:\"\u0000*\u0000pii\";s:0:\"\";s:7:\"\u0000*\u0000pmid\";s:0:\"\";s:9:\"\u0000*\u0000atitle\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:9:\"\u0000*\u0000jtitle\";s:30:\"IEEE transactions on computers\";s:9:\"\u0000*\u0000stitle\";s:18:\"IEEE trans. comput\";s:7:\"\u0000*\u0000date\";s:4:\"1986\";s:9:\"\u0000*\u0000volume\";s:2:\"35\";s:8:\"\u0000*\u0000issue\";s:1:\"8\";s:8:\"\u0000*\u0000spage\";s:3:\"742\";s:8:\"\u0000*\u0000epage\";s:3:\"754\";s:8:\"\u0000*\u0000pages\";s:0:\"\";s:7:\"\u0000*\u0000issn\";s:9:\"0018-9340\";s:8:\"\u0000*\u0000eissn\";s:0:\"\";s:9:\"\u0000*\u0000aulast\";s:5:\"REDDY\";s:10:\"\u0000*\u0000aufirst\";s:4:\"S. M\";s:9:\"\u0000*\u0000auinit\";s:0:\"\";s:10:\"\u0000*\u0000auinitm\";s:0:\"\";s:5:\"\u0000*\u0000au\";a:1:{i:0;s:11:\"REDDY, M. K\";}s:9:\"\u0000*\u0000aucorp\";s:0:\"\";s:7:\"\u0000*\u0000isbn\";s:0:\"\";s:8:\"\u0000*\u0000coden\";s:6:\"ITCOB4\";s:8:\"\u0000*\u0000genre\";s:7:\"article\";s:7:\"\u0000*\u0000part\";s:0:\"\";s:9:\"\u0000*\u0000btitle\";s:0:\"\";s:8:\"\u0000*\u0000title\";s:84:\"Testable realizations for FET stuck-open faults in CMOS combinational logic circuits\";s:8:\"\u0000*\u0000place\";s:12:\"New York, NY\";s:6:\"\u0000*\u0000pub\";s:49:\"Institute of Electrical and Electronics Engineers\";s:10:\"\u0000*\u0000edition\";s:0:\"\";s:9:\"\u0000*\u0000tpages\";s:0:\"\";s:9:\"\u0000*\u0000series\";s:0:\"\";s:8:\"\u0000*\u0000proxy\";s:30:\"http:\/\/proxyout.inist.fr:8080\/\";s:12:\"\u0000*\u0000integrite\";b:1;}"
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