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Digraph relaxation for 2-dimensional placement of IC blocks

Author
CIESIELSKI, M. J1 ; KINNEN, E
[1] GTE Laboratories inc., Waltham MA 02254, United States
Source

IEEE transactions on computer-aided design of integrated circuits and systems. 1987, Vol 6, Num 1, pp 55-66 ; ref : 15 ref

CODEN
ITCSDI
ISSN
0278-0070
Scientific domain
Electronics
Publisher
Institute of Electrical and Electronics Engineers, New York, NY
Publication country
United States
Document type
Article
Language
English
Keyword (fr)
Architecture Bloc Circuit intégré Conception assistée Flexibilité Minimisation Modèle 2 dimensions Optimisation Surface Théorie graphe
Keyword (en)
Architecture Block Integrated circuit Computer aided design Flexibility Minimization Two dimensional model Optimization Surface Graph theory
Keyword (es)
Arquitectura Bloque Circuito integrado Concepción asistida Flexibilidad Minimización Modelo 2 dimensiones Optimizacion Superficie Teoría grafo
Classification
Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03F Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices / 001D03F06 Integrated circuits

Discipline
Electronics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
8072310

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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