The architecture of a programmable systolic chip
- Author
- FISHER, A. L1 ; KUNG, H. T; MONIER, L. M; YASUNORI DOHI
[1] Carnegie-Mellon univ., dep. computer sci., Pittsburgh PA 15213, United States - Source
Journal of VLSI and computer systems. 1984, Vol 1, Num 2, pp 153-169 ; ref : 20 ref
- ISSN
- 0733-5644
- Scientific domain
- Electronics; Computer science
- Publisher
- Computer Science Press, Rockville, MD
- Publication country
- United States
- Document type
- Article
- Language
- English
- Keyword (fr)
- Architecture système Microprocesseur Multiprocesseur Processeur systolique Puce Technologie NMOS CMU Puce systolique programmable
- Keyword (en)
- System architecture Microprocessor Multiprocessor Systolic processor Chip NMOS technology
- Classification
- Pascal
- 001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics / 001D03J Hardware / 001D03J07 Computers, microcomputers
- Discipline
- Electronics
- Origin
- Inist-CNRS
- Database
- PASCAL
- INIST identifier
- 8937947
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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