FUNDAMENTAL LIMITATIONS IN MICROELECTRONICS. I. MOS TECHNOLOGY
- Autor
- HOENEISEN B; MEAD CA
CALIFORNIA INST. TECHNOL., PASADENA, CALIF., U.S.A. - Fuente
- SOLID-STATE ELECTRON.; G.B.; DA. 1972; VOL. 15; NO 7; PP. 819-829; BIBL. 14 REF.
- Tipo de documento
- Serial Issue
- Idioma
- English
- Palabra clave (fr)
- FABRICATION MICROELECTRONIQUE TECHNOLOGIE MOS DISRUPTION ELECTRIQUE TRANSISTOR MOS TRANSISTOR EFFET CHAMP INTEGRATION GRANDE ECHELLE CIRCUIT INTEGRE CIRCUIT INTEGRE GRANDE ECHELLE LIMITE ELECTROMAGNETISME ELECTRONIQUE
- Palabra clave (in)
- ELECTROMAGNETISM ELECTRONICS
- Palabra clave (es)
- ELECTROMAGNETISMO ELECTRONICA
- Clasificación
- Disciplina
- Electronics
- Procedencia
- Inist-CNRS
- Base de datos
- PASCAL
- Identificador INIST
- PASCAL7314505364
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
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