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LOGIC ANALYZER FOR MAINTENANCE PLANNING: AUTOMATIC TEST GENERATION FOR ASYNCHRONOUS DIGITAL CIRCUITS.

Other title
ANALYSEUR DE CIRCUITS LOGIQUES POUR LA PLANIFICATION DE LA MAINTENANCE: CREATION AUTOMATIQUE DE TESTS DE CIRCUITS NUMERIQUES ASYNCHRONES (fr)
Author
CHAPPELL SG
Source
BELL SYST. TECH. J.; U.S.A.; DA. 1974; VOL. 53; NO 8; PP. 1477-1503; BIBL. 9 REF.
Document type
Article
Language
English
Keyword (fr)
ANALYSEUR CIRCUIT CIRCUIT LOGIQUE PLANIFICATION MAINTENANCE CIRCUIT NUMERIQUE CIRCUIT ASYNCHRONE ESSAI ANALYSE CIRCUIT CONCEPTION CIRCUIT CIRCUIT SEQUENTIEL ESSAI AUTOMATIQUE ELECTROMAGNETISME ELECTRONIQUE INFORMATIQUE MATHEMATIQUES APPLIQUEES
Keyword (en)
ELECTROMAGNETISM ELECTRONICS COMPUTER SCIENCES APPLIED MATHEMATICS
Keyword (es)
ELECTROMAGNETISMO ELECTRONICA INFORMATICA MATEMATICAS APPLICADAS
Classification
Pascal
001 Exact sciences and technology / 001A Sciences and techniques of general use / 001A02 Mathematics

Pascal
001 Exact sciences and technology / 001D Applied sciences / 001D03 Electronics

Discipline
Electronics Mathematics
Origin
Inist-CNRS
Database
PASCAL
INIST identifier
PASCAL7530091726

Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS

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